Lines Matching refs:val
46 spr_tcp_state(val("t_state")), in t4_display_tcb_aux_0()
47 val("t_state"), in t4_display_tcb_aux_0()
48 spr_ip_version(val("ip_version")), in t4_display_tcb_aux_0()
49 val("lock_tid"), in t4_display_tcb_aux_0()
50 val("init") in t4_display_tcb_aux_0()
53 val("l2t_ix"), in t4_display_tcb_aux_0()
54 val("smac_sel"), in t4_display_tcb_aux_0()
55 val("tos") in t4_display_tcb_aux_0()
58 val("t_maxseg"), val("recv_scale"), in t4_display_tcb_aux_0()
59 val("recv_tstmp"), val("recv_sack")); in t4_display_tcb_aux_0()
64 val("timer"), val("dack_timer")); in t4_display_tcb_aux_0()
66 val("mod_schd_tx"), in t4_display_tcb_aux_0()
67 val("mod_schd_rx"), in t4_display_tcb_aux_0()
68 ((val("mod_schd_reason2")<<2) | (val("mod_schd_reason1")<<1) | in t4_display_tcb_aux_0()
69 val("mod_schd_reason0")) in t4_display_tcb_aux_0()
74 val("max_rt"), val("t_rxtshift"), in t4_display_tcb_aux_0()
75 val("keepalive")); in t4_display_tcb_aux_0()
77 val("timestamp_offset"),val("timestamp")); in t4_display_tcb_aux_0()
81 val("t_rtt_ts_recent_age"), val("t_rtseq_recent")); in t4_display_tcb_aux_0()
83 val("t_srtt"),val("t_rttvar")); in t4_display_tcb_aux_0()
92 val("snd_una"),val("snd_nxt"), in t4_display_tcb_aux_0()
93 val("snd_max"),val("tx_max")); in t4_display_tcb_aux_0()
95 val("core_fin"), SEQ_SUB(val("tx_max"),val("snd_una")) in t4_display_tcb_aux_0()
97 if (val("recv_scale") && !val("active_open")) { in t4_display_tcb_aux_0()
99 val("rcv_adv"), val("rcv_scale"), in t4_display_tcb_aux_0()
100 val("rcv_adv") << val("rcv_scale"), in t4_display_tcb_aux_0()
101 val("recv_scale"), val("rcv_scale"), val("active_open")); in t4_display_tcb_aux_0()
104 val("rcv_adv"), val("rcv_scale"), in t4_display_tcb_aux_0()
105 val("recv_scale"), val("active_open")); in t4_display_tcb_aux_0()
109 val("snd_cwnd") , val("snd_ssthresh"), val("snd_rec") in t4_display_tcb_aux_0()
116 spr_cctrl_sel(val("cctrl_sel0"),val("cctrl_sel1")), in t4_display_tcb_aux_0()
117 val("cctrl_ecn"), val("cctrl_ece"), val("cctrl_cwr"), in t4_display_tcb_aux_0()
118 val("cctrl_rfr")); in t4_display_tcb_aux_0()
120 val("t_dupacks"), val("dupack_count_odd"),val("fast_recovery")); in t4_display_tcb_aux_0()
122 val("core_more"),val("core_urg"),val("core_push")); in t4_display_tcb_aux_0()
123 PR(" core_flush %u\n",val("core_flush")); in t4_display_tcb_aux_0()
125 val("nagle"), val("ssws_disabled"), val("turbo")); in t4_display_tcb_aux_0()
126 PR(" tx_pdu_out %u\n",val("tx_pdu_out")); in t4_display_tcb_aux_0()
128 val("tx_pace_auto"),val("tx_pace_fixed"),val("tx_queue")); in t4_display_tcb_aux_0()
131 PR(" tx_quiesce %u\n",val("tx_quiesce")); in t4_display_tcb_aux_0()
133 val("tx_channel"), in t4_display_tcb_aux_0()
134 (val("tx_channel")>>1)&1, in t4_display_tcb_aux_0()
135 val("tx_channel")&1 in t4_display_tcb_aux_0()
142 val("tx_hdr_ptr"),val("tx_last_ptr"),val("tx_compact")); in t4_display_tcb_aux_0()
149 val("ts_last_ack_sent"),val("rx_compact")); in t4_display_tcb_aux_0()
151 val("rcv_nxt"), val("rx_hdr_offset")); in t4_display_tcb_aux_0()
153 val("rx_frag0_start_idx"), in t4_display_tcb_aux_0()
154 val("rx_frag0_len"), in t4_display_tcb_aux_0()
155 val("rx_ptr")); in t4_display_tcb_aux_0()
157 val("rx_frag1_start_idx_offset"), in t4_display_tcb_aux_0()
158 val("rx_frag1_len")); in t4_display_tcb_aux_0()
163 …if (val("ulp_type")!=4) { /* RDMA has FRAG1 idx && len, but no ptr? Should I not display frag1 at… in t4_display_tcb_aux_0()
164 PR("frag1_ptr 0x%-8x\n",val("rx_frag1_ptr")); in t4_display_tcb_aux_0()
170 if (val("ulp_type") !=6 && val("ulp_type") != 5 && val("ulp_type") !=4) { in t4_display_tcb_aux_0()
172 val("rx_frag2_start_idx_offset"), in t4_display_tcb_aux_0()
173 val("rx_frag2_len"), in t4_display_tcb_aux_0()
174 val("rx_frag2_ptr")); in t4_display_tcb_aux_0()
176 val("rx_frag3_start_idx_offset"), in t4_display_tcb_aux_0()
177 val("rx_frag3_len"), in t4_display_tcb_aux_0()
178 val("rx_frag3_ptr")); in t4_display_tcb_aux_0()
187 val("peer_fin"),val("rx_pdu_out"), val("pdu_len")); in t4_display_tcb_aux_0()
192 if (val("recv_scale")) { in t4_display_tcb_aux_0()
194 val("rcv_wnd"), val("snd_scale"), in t4_display_tcb_aux_0()
195 val("rcv_wnd") >> val("snd_scale"), in t4_display_tcb_aux_0()
196 val("recv_scale")); in t4_display_tcb_aux_0()
199 val("rcv_wnd"), val("snd_scale"), in t4_display_tcb_aux_0()
200 val("recv_scale")); in t4_display_tcb_aux_0()
207 val("dack_mss"),val("dack"),val("dack_not_acked")); in t4_display_tcb_aux_0()
209 val("rcv_coalesce_enable"), in t4_display_tcb_aux_0()
210 val("rcv_coalesce_push"), in t4_display_tcb_aux_0()
211 val("rcv_coalesce_last_psh"), in t4_display_tcb_aux_0()
212 val("rcv_coalesce_heartbeat")); in t4_display_tcb_aux_0()
215 val("rx_channel"), val("rx_quiesce"), in t4_display_tcb_aux_0()
216 val("rx_flow_control_disable")); in t4_display_tcb_aux_0()
218 val("rx_flow_control_ddp")); in t4_display_tcb_aux_0()
223 ((val("pend_ctl2")<<2) | (val("pend_ctl1")<<1) | in t4_display_tcb_aux_0()
224 val("pend_ctl0")), in t4_display_tcb_aux_0()
225 val("unused"),val("main_slush")); in t4_display_tcb_aux_0()
227 val("migrating"), in t4_display_tcb_aux_0()
228 val("ask_mode"), val("non_offload"), val("rss_info")); in t4_display_tcb_aux_0()
230 val("ulp_type"), spr_ulp_type(val("ulp_type")),val("ulp_raw")); in t4_display_tcb_aux_0()
232 val("rdma_error"), val("rdma_flm_error")); in t4_display_tcb_aux_0()
242 val("aux1_slush0"), val("aux1_slush1")); in t4_display_tcb_aux_1()
243 PR(" pdu_hdr_len %u\n",val("pdu_hdr_len")); in t4_display_tcb_aux_1()
255 val("qp_id"), val("pd_id"),val("stag")); in t4_display_tcb_aux_2()
257 val("irs_ulp"),val("iss_ulp")); in t4_display_tcb_aux_2()
259 val("tx_pdu_len")); in t4_display_tcb_aux_2()
261 val("cq_idx_sq"),val("cq_idx_rq")); in t4_display_tcb_aux_2()
263 val("rq_start"),val("rq_msn"),val("rq_max_offset"), in t4_display_tcb_aux_2()
264 val("rq_write_ptr")); in t4_display_tcb_aux_2()
266 val("ord_l_bit_vld"),val("rdmap_opcode")); in t4_display_tcb_aux_2()
268 val("tx_flush"),val("tx_oos_rxmt"),val("tx_oos_txmt")); in t4_display_tcb_aux_2()
281 val("aux3_slush"),val("ddp_buf0_unused"),val("ddp_buf1_unused"), in t4_display_tcb_aux_3()
282 val("ddp_main_unused")); in t4_display_tcb_aux_3()
290 val("ddp_off"),val("ddp_active_buf"),val("ddp_indicate_out"), in t4_display_tcb_aux_3()
291 val("ddp_wait_frag"),val("ddp_rx2tx"),val("ddp_buf_inf") in t4_display_tcb_aux_3()
300 val("ddp_buf0_indicate"), in t4_display_tcb_aux_3()
301 val("ddp_pshf_enable_0"), val("ddp_push_disable_0"), in t4_display_tcb_aux_3()
302 val("ddp_buf0_flush"), val("ddp_psh_no_invalidate0") in t4_display_tcb_aux_3()
305 val("ddp_buf1_indicate"), in t4_display_tcb_aux_3()
306 val("ddp_pshf_enable_1"), val("ddp_push_disable_1"), in t4_display_tcb_aux_3()
307 val("ddp_buf1_flush"), val("ddp_psh_no_invalidate1") in t4_display_tcb_aux_3()
321 val("ddp_buf0_valid"),val("rx_ddp_buf0_offset"), in t4_display_tcb_aux_3()
322 val("rx_ddp_buf0_len"),val("rx_ddp_buf0_tag") in t4_display_tcb_aux_3()
326 if (0==val("ddp_off") && 1==val("ddp_buf0_valid") && 0==val("ddp_active_buf")) { in t4_display_tcb_aux_3()
334 val("ddp_buf1_valid"),val("rx_ddp_buf1_offset"), in t4_display_tcb_aux_3()
335 val("rx_ddp_buf1_len"),val("rx_ddp_buf1_tag") in t4_display_tcb_aux_3()
341 if (0==val("ddp_off") && 1==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) { in t4_display_tcb_aux_3()
352 if (1==val("ddp_off")) { in t4_display_tcb_aux_3()
354 } else if (1==val("ddp_buf0_valid") && 0==val("ddp_active_buf")) { in t4_display_tcb_aux_3()
357 val("rx_ddp_buf0_len"),val("rx_ddp_buf0_offset"), in t4_display_tcb_aux_3()
358 val("rx_ddp_buf0_len")-val("rx_ddp_buf0_offset") in t4_display_tcb_aux_3()
360 if (1==val("ddp_buf1_valid")) { in t4_display_tcb_aux_3()
362 val("rx_ddp_buf1_len"),val("rx_ddp_buf1_offset"), in t4_display_tcb_aux_3()
363 val("rx_ddp_buf1_len")-val("rx_ddp_buf1_offset") in t4_display_tcb_aux_3()
366 } else if (1==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) { in t4_display_tcb_aux_3()
369 val("rx_ddp_buf1_len"),val("rx_ddp_buf1_offset"), in t4_display_tcb_aux_3()
370 val("rx_ddp_buf1_len")-val("rx_ddp_buf1_offset") in t4_display_tcb_aux_3()
372 if (1==val("ddp_buf0_valid")) { in t4_display_tcb_aux_3()
374 val("rx_ddp_buf0_len"),val("rx_ddp_buf0_offset"), in t4_display_tcb_aux_3()
375 val("rx_ddp_buf0_len")-val("rx_ddp_buf0_offset") in t4_display_tcb_aux_3()
378 } else if (0==val("ddp_buf0_valid") && 1==val("ddp_buf1_valid") && 0==val("ddp_active_buf")) { in t4_display_tcb_aux_3()
380 } else if (1==val("ddp_buf0_valid") && 0==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) { in t4_display_tcb_aux_3()
388 if (0==val("ddp_indicate_out")) { in t4_display_tcb_aux_3()
389 if (0==val("ddp_buf0_indicate") && 0==val("ddp_buf1_indicate")) { in t4_display_tcb_aux_3()
391 if (0==val("rx_hdr_offset")) { in t4_display_tcb_aux_3()
395 val("rx_hdr_offset")); in t4_display_tcb_aux_3()
400 } else if (1==val("ddp_indicate_out")) { in t4_display_tcb_aux_3()
402 if (0==val("rx_hdr_offset")) { in t4_display_tcb_aux_3()
406 val("rx_hdr_offset")); in t4_display_tcb_aux_3()