Lines Matching full:pr
44 PR("STATE:\n"); in t4_display_tcb_aux_0()
45 PR(" %-12s (%-2u), %s, lock_tid %u, init %u\n", in t4_display_tcb_aux_0()
52 PR(" l2t_ix 0x%x, smac sel 0x%x, tos 0x%x\n", in t4_display_tcb_aux_0()
57 PR(" maxseg %u, recv_scaleflag %u, recv_tstmp %u, recv_sack %u\n", in t4_display_tcb_aux_0()
62 PR("TIMERS:\n"); /* **************************************** */ in t4_display_tcb_aux_0()
63 PR(" timer %u, dack_timer %u\n", in t4_display_tcb_aux_0()
65 PR(" mod_schd: tx: %u, rx: %u, reason 0x%1x\n", in t4_display_tcb_aux_0()
73 PR(" max_rt %-2u, rxtshift %u, keepalive %u\n", in t4_display_tcb_aux_0()
76 PR(" timestamp_offset 0x%x, timestamp 0x%x\n", in t4_display_tcb_aux_0()
80 PR(" t_rtt_ts_recent_age %u t_rttseq_recent %u\n", in t4_display_tcb_aux_0()
82 PR(" t_srtt %u, t_rttvar %u\n", in t4_display_tcb_aux_0()
90 PR("TRANSMIT BUFFER:\n"); /* *************************** */ in t4_display_tcb_aux_0()
91 PR(" snd_una %u, snd_nxt %u, snd_max %u, tx_max %u\n", in t4_display_tcb_aux_0()
94 PR(" core_fin %u, tx_hdr_offset %u\n", in t4_display_tcb_aux_0()
98 PR(" rcv_adv %-5u << %-2u == %u (recv_scaleflag %u rcv_scale %u active open %u)\n", in t4_display_tcb_aux_0()
103 PR(" rcv_adv %-5u (rcv_scale %-2u recv_scaleflag %u active_open %u)\n", in t4_display_tcb_aux_0()
108 PR(" snd_cwnd %-5u snd_ssthresh %u snd_rec %u\n", in t4_display_tcb_aux_0()
115 PR(" cctrl: sel %s, ecn %u, ece %u, cwr %u, rfr %u\n", in t4_display_tcb_aux_0()
119 PR(" t_dupacks %u, dupack_count_odd %u, fast_recovery %u\n", in t4_display_tcb_aux_0()
121 PR(" core_more %u, core_urg, %u core_push %u,", in t4_display_tcb_aux_0()
123 PR(" core_flush %u\n",val("core_flush")); in t4_display_tcb_aux_0()
124 PR(" nagle %u, ssws_disable %u, turbo %u,", in t4_display_tcb_aux_0()
126 PR(" tx_pdu_out %u\n",val("tx_pdu_out")); in t4_display_tcb_aux_0()
127 PR(" tx_pace_auto %u, tx_pace_fixed %u, tx_queue %u", in t4_display_tcb_aux_0()
131 PR(" tx_quiesce %u\n",val("tx_quiesce")); in t4_display_tcb_aux_0()
132 PR(" tx_channel %u, tx_channel1 %u, tx_channel0 %u\n", in t4_display_tcb_aux_0()
141 PR(" tx_hdr_ptr 0x%-6x tx_last_ptr 0x%-6x tx_compact %u\n", in t4_display_tcb_aux_0()
147 PR("RECEIVE BUFFER:\n"); /* *************************** */ in t4_display_tcb_aux_0()
148 PR(" last_ack_sent %-10u rx_compact %u\n", in t4_display_tcb_aux_0()
150 PR(" rcv_nxt %-10u hdr_off %-10u\n", in t4_display_tcb_aux_0()
152 PR(" frag0_idx %-10u length %-10u frag0_ptr 0x%-8x\n", in t4_display_tcb_aux_0()
156 PR(" frag1_idx %-10u length %-10u ", in t4_display_tcb_aux_0()
164 PR("frag1_ptr 0x%-8x\n",val("rx_frag1_ptr")); in t4_display_tcb_aux_0()
166 PR("\n"); in t4_display_tcb_aux_0()
171 PR(" frag2_idx %-10u length %-10u frag2_ptr 0x%-8x\n", in t4_display_tcb_aux_0()
175 PR(" frag3_idx %-10u length %-10u frag3_ptr 0x%-8x\n", in t4_display_tcb_aux_0()
186 PR(" peer_fin %u, rx_pdu_out %u, pdu_len %u\n", in t4_display_tcb_aux_0()
193 PR(" rcv_wnd %u >> snd_scale %u == %u, recv_scaleflag = %u\n", in t4_display_tcb_aux_0()
198 PR(" rcv_wnd %u. (snd_scale %u, recv_scaleflag = %u)\n", in t4_display_tcb_aux_0()
206 PR(" dack_mss %u dack %u, dack_not_acked: %u\n", in t4_display_tcb_aux_0()
208 PR(" rcv_coal %u rcv_co_psh %u rcv_co_last_psh %u heart %u\n", in t4_display_tcb_aux_0()
214 PR(" rx_channel %u rx_quiesce %u rx_flow_ctrl_dis %u,", in t4_display_tcb_aux_0()
217 PR(" rx_flow_ctrl_ddp %u\n", in t4_display_tcb_aux_0()
221 PR("MISCELLANEOUS:\n"); /* *************************** */ in t4_display_tcb_aux_0()
222 PR(" pend_ctl: 0x%1x, unused_flags: 0x%x, main_slush: 0x%x\n", in t4_display_tcb_aux_0()
226 PR(" Migrating %u, ask_mode %u, non_offload %u, rss_info %u\n", in t4_display_tcb_aux_0()
229 PR(" ULP: ulp_type %u (%s), ulp_raw %u\n", in t4_display_tcb_aux_0()
231 PR(" RDMA: error %u, flm_err %u\n", in t4_display_tcb_aux_0()
241 PR(" aux1_slush0: 0x%x aux1_slush1 0x%x\n", in t4_display_tcb_aux_1()
243 PR(" pdu_hdr_len %u\n",val("pdu_hdr_len")); in t4_display_tcb_aux_1()
254 PR(" qp_id %u, pd_id %u, stag %u\n", in t4_display_tcb_aux_2()
256 PR(" irs_ulp %u, iss_ulp %u\n", in t4_display_tcb_aux_2()
258 PR(" tx_pdu_len %u\n", in t4_display_tcb_aux_2()
260 PR(" cq_idx_sq %u, cq_idx_rq %u\n", in t4_display_tcb_aux_2()
262 PR(" rq_start %u, rq_MSN %u, rq_max_off %u, rq_write_ptr %u\n", in t4_display_tcb_aux_2()
265 PR(" L_valid %u, rdmap opcode %u\n", in t4_display_tcb_aux_2()
267 PR(" tx_flush: %u, tx_oos_rxmt %u, tx_oos_txmt %u\n", in t4_display_tcb_aux_2()
280 PR(" aux3_slush: 0x%x, unused: buf0 0x%x, buf1: 0x%x, main: 0x%x\n", in t4_display_tcb_aux_3()
288 PR(" DDP: DDPOFF ActBuf IndOut WaitFrag Rx2Tx BufInf\n"); in t4_display_tcb_aux_3()
289 PR(" %u %u %u %u %u %u\n", in t4_display_tcb_aux_3()
298 PR(" Ind PshfEn PushDis Flush NoInvalidate\n"); in t4_display_tcb_aux_3()
299 PR(" Buf0: %u %u %u %u %u\n", in t4_display_tcb_aux_3()
304 PR(" Buf1: %u %u %u %u %u\n", in t4_display_tcb_aux_3()
319 PR(" Valid Offset Length Tag\n"); in t4_display_tcb_aux_3()
320 PR(" Buf0: %u 0x%6.6x 0x%6.6x 0x%8.8x", in t4_display_tcb_aux_3()
327 PR(" (Active)\n"); in t4_display_tcb_aux_3()
329 PR(" (Inactive)\n"); in t4_display_tcb_aux_3()
333 PR(" Buf1: %u 0x%6.6x 0x%6.6x 0x%8.8x", in t4_display_tcb_aux_3()
342 PR(" (Active)\n"); in t4_display_tcb_aux_3()
344 PR(" (Inactive)\n"); in t4_display_tcb_aux_3()
353 PR(" DDP is off (which also disables indicate)\n"); in t4_display_tcb_aux_3()
355 PR(" Data being DDP'ed to buf 0, "); in t4_display_tcb_aux_3()
356 PR("which has %u - %u = %u bytes of space left\n", in t4_display_tcb_aux_3()
361 PR(" And buf1, which is also valid, has %u - %u = %u bytes of space left\n", in t4_display_tcb_aux_3()
367 PR(" Data being DDP'ed to buf 1, "); in t4_display_tcb_aux_3()
368 PR("which has %u - %u = %u bytes of space left\n", in t4_display_tcb_aux_3()
373 PR(" And buf0, which is also valid, has %u - %u = %u bytes of space left\n", in t4_display_tcb_aux_3()
379 PR(" !!! Invalid DDP buf 1 valid, but buf 0 active.\n"); in t4_display_tcb_aux_3()
381 PR(" !!! Invalid DDP buf 0 valid, but buf 1 active.\n"); in t4_display_tcb_aux_3()
383 PR(" DDP is enabled, but no buffers are active && valid.\n"); in t4_display_tcb_aux_3()
390 PR(" 0 length Indicate buffers "); in t4_display_tcb_aux_3()
392 PR("will cause new data to be held in PMRX.\n"); in t4_display_tcb_aux_3()
394 PR("is causing %u bytes to be held in PMRX\n", in t4_display_tcb_aux_3()
398 PR(" Data being indicated to host\n"); in t4_display_tcb_aux_3()
401 PR(" Indicate is off, which "); in t4_display_tcb_aux_3()
403 PR("will cause new data to be held in PMRX.\n"); in t4_display_tcb_aux_3()
405 PR("is causing %u bytes to be held in PMRX\n", in t4_display_tcb_aux_3()