Lines Matching +full:enable +full:- +full:modem +full:- +full:interrupt
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
87 uint8_t ier; /* Interrupt enable register (R/W) */
89 uint8_t mcr; /* Modem control register (R/W) */
91 uint8_t msr; /* Modem status register (R/W) */
98 bool thre_int_pending; /* THRE interrupt pending */
137 * The IIR returns a prioritized interrupt reason:
138 * - receive data available
139 * - transmit holding register empty
140 * - modem status change
142 * Return an interrupt reason if one is available.
148 if ((sc->lsr & LSR_OE) != 0 && (sc->ier & IER_ERLS) != 0)
150 else if (uart_rxfifo_numchars(sc->backend) > 0 &&
151 (sc->ier & IER_ERXRDY) != 0)
153 else if (sc->thre_int_pending && (sc->ier & IER_ETXRDY) != 0)
155 else if ((sc->msr & MSR_DELTA_MASK) != 0 && (sc->ier & IER_EMSC) != 0)
167 sc->dll = divisor;
168 sc->dlh = divisor >> 16;
169 sc->msr = modem_status(sc->mcr);
171 uart_rxfifo_reset(sc->backend, 1);
176 * interrupt condition to report to the processor.
186 (*sc->intr_deassert)(sc->arg);
188 (*sc->intr_assert)(sc->arg);
206 uart_softc_lock(sc->backend);
208 loopback = (sc->mcr & MCR_LOOPBACK) != 0;
209 uart_rxfifo_drain(sc->backend, loopback);
213 uart_softc_unlock(sc->backend);
222 uart_softc_lock(sc->backend);
227 if ((sc->lcr & LCR_DLAB) != 0) {
229 sc->dll = value;
234 sc->dlh = value;
241 if (uart_rxfifo_putchar(sc->backend, value,
242 (sc->mcr & MCR_LOOPBACK) != 0))
243 sc->lsr |= LSR_OE;
244 sc->thre_int_pending = true;
247 /* Set pending when IER_ETXRDY is raised (edge-triggered). */
248 if ((sc->ier & IER_ETXRDY) == 0 && (value & IER_ETXRDY) != 0)
249 sc->thre_int_pending = true;
251 * Apply mask so that bits 4-7 are 0
252 * Also enables bits 0-3 only if they're 1
254 sc->ier = value & 0x0F;
261 if ((sc->fcr & FCR_ENABLE) ^ (value & FCR_ENABLE)) {
263 uart_rxfifo_size(sc->backend) : 1;
264 uart_rxfifo_reset(sc->backend, fifosz);
272 sc->fcr = 0;
275 uart_rxfifo_reset(sc->backend,
276 uart_rxfifo_size(sc->backend));
278 sc->fcr = value &
283 sc->lcr = value;
286 /* Apply mask so that bits 5-7 are 0 */
287 sc->mcr = value & 0x1F;
288 msr = modem_status(sc->mcr);
295 if ((msr & MSR_CTS) ^ (sc->msr & MSR_CTS))
296 sc->msr |= MSR_DCTS;
297 if ((msr & MSR_DSR) ^ (sc->msr & MSR_DSR))
298 sc->msr |= MSR_DDSR;
299 if ((msr & MSR_DCD) ^ (sc->msr & MSR_DCD))
300 sc->msr |= MSR_DDCD;
301 if ((sc->msr & MSR_RI) != 0 && (msr & MSR_RI) == 0)
302 sc->msr |= MSR_TERI;
308 sc->msr &= MSR_DELTA_MASK;
309 sc->msr |= msr;
319 * As far as I can tell MSR is a read-only register.
323 sc->scr = value;
331 uart_softc_unlock(sc->backend);
339 uart_softc_lock(sc->backend);
344 if ((sc->lcr & LCR_DLAB) != 0) {
346 reg = sc->dll;
351 reg = sc->dlh;
358 reg = uart_rxfifo_getchar(sc->backend);
361 reg = sc->ier;
364 iir = (sc->fcr & FCR_ENABLE) ? IIR_FIFO_MASK : 0;
372 sc->thre_int_pending = false;
379 reg = sc->lcr;
382 reg = sc->mcr;
386 sc->lsr |= LSR_TEMT | LSR_THRE;
389 if (uart_rxfifo_numchars(sc->backend) > 0)
390 sc->lsr |= LSR_RXRDY;
392 sc->lsr &= ~LSR_RXRDY;
394 reg = sc->lsr;
397 sc->lsr &= ~LSR_OE;
403 reg = sc->msr;
404 sc->msr &= ~MSR_DELTA_MASK;
407 reg = sc->scr;
416 uart_softc_unlock(sc->backend);
426 return (-1);
443 sc->arg = arg;
444 sc->intr_assert = intr_assert;
445 sc->intr_deassert = intr_deassert;
446 sc->backend = uart_init();
456 return (uart_tty_open(sc->backend, device, uart_drain, sc));
466 SNAPSHOT_VAR_OR_LEAVE(sc->data, meta, ret, done);
467 SNAPSHOT_VAR_OR_LEAVE(sc->ier, meta, ret, done);
468 SNAPSHOT_VAR_OR_LEAVE(sc->lcr, meta, ret, done);
469 SNAPSHOT_VAR_OR_LEAVE(sc->mcr, meta, ret, done);
470 SNAPSHOT_VAR_OR_LEAVE(sc->lsr, meta, ret, done);
471 SNAPSHOT_VAR_OR_LEAVE(sc->msr, meta, ret, done);
472 SNAPSHOT_VAR_OR_LEAVE(sc->fcr, meta, ret, done);
473 SNAPSHOT_VAR_OR_LEAVE(sc->scr, meta, ret, done);
475 SNAPSHOT_VAR_OR_LEAVE(sc->dll, meta, ret, done);
476 SNAPSHOT_VAR_OR_LEAVE(sc->dlh, meta, ret, done);
478 ret = uart_rxfifo_snapshot(sc->backend, meta);
480 sc->thre_int_pending = 1;