Lines Matching +full:prop +full:-
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (c) 2024-2025 Ruslan Bukin <br@bsdpad.com>
53 #define SET_PROP_U32(prop, idx, val) \ argument
54 ((uint32_t *)(prop))[(idx)] = cpu_to_fdt32(val)
55 #define SET_PROP_U64(prop, idx, val) \ argument
56 ((uint64_t *)(prop))[(idx)] = cpu_to_fdt64(val)
100 fdt_property_string(fdt, "mmu-type", "riscv,sv39"); in add_cpu()
102 fdt_begin_node(fdt, "interrupt-controller"); in add_cpu()
104 fdt_property_u32(fdt, "#address-cells", 2); in add_cpu()
105 fdt_property_u32(fdt, "#interrupt-cells", 1); in add_cpu()
106 fdt_property(fdt, "interrupt-controller", NULL, 0); in add_cpu()
107 fdt_property_string(fdt, "compatible", "riscv,cpu-intc"); in add_cpu()
119 /* XXX: Needed given the root #address-cells? */ in add_cpus()
120 fdt_property_u32(fdt, "#address-cells", 1); in add_cpus()
121 fdt_property_u32(fdt, "#size-cells", 0); in add_cpus()
123 fdt_property_u32(fdt, "timebase-frequency", 1000000); in add_cpus()
152 fdt_property_u32(fdt, "#address-cells", 2); in fdt_init()
153 fdt_property_u32(fdt, "#size-cells", 2); in fdt_init()
156 fdt_property_string(fdt, "stdout-path", "serial0:115200n8"); in fdt_init()
181 void *fdt, *prop; in fdt_add_aplic() local
186 snprintf(node_name, sizeof(node_name), "interrupt-controller@%lx", in fdt_add_aplic()
192 fdt_property(fdt, "interrupt-controller", NULL, 0); in fdt_add_aplic()
194 fdt_property(fdt, "msi-controller", NULL, 0); in fdt_add_aplic()
196 /* XXX: Needed given the root #address-cells? */ in fdt_add_aplic()
197 fdt_property_u32(fdt, "#address-cells", 2); in fdt_add_aplic()
198 fdt_property_u32(fdt, "#interrupt-cells", 2); in fdt_add_aplic()
199 fdt_property_placeholder(fdt, "reg", 2 * sizeof(uint64_t), &prop); in fdt_add_aplic()
200 SET_PROP_U64(prop, 0, mem_base); in fdt_add_aplic()
201 SET_PROP_U64(prop, 1, mem_size); in fdt_add_aplic()
204 fdt_property_placeholder(fdt, "interrupts-extended", in fdt_add_aplic()
205 2 * ncpu * sizeof(uint32_t), &prop); in fdt_add_aplic()
207 SET_PROP_U32(prop, i * 2 + 0, intc_phandles[i]); in fdt_add_aplic()
208 SET_PROP_U32(prop, i * 2 + 1, IRQ_EXTERNAL_SUPERVISOR); in fdt_add_aplic()
210 fdt_property_u32(fdt, "riscv,num-sources", 63); in fdt_add_aplic()
214 fdt_property_u32(fdt, "interrupt-parent", aplic_phandle); in fdt_add_aplic()
231 fdt_property_u32(fdt, "clock-frequency", 3686400); in fdt_add_uart()
232 fdt_property_u32(fdt, "interrupt-parent", aplic_phandle); in fdt_add_uart()
249 void *fdt, *prop; in fdt_add_pcie() local
257 fdt_property_string(fdt, "compatible", "pci-host-ecam-generic"); in fdt_add_pcie()
258 fdt_property_u32(fdt, "#address-cells", 3); in fdt_add_pcie()
259 fdt_property_u32(fdt, "#size-cells", 2); in fdt_add_pcie()
261 fdt_property_u64(fdt, "bus-range", (0ul << 32) | 1); in fdt_add_pcie()
264 2 * 7 * sizeof(uint32_t), &prop); in fdt_add_pcie()
265 SET_PROP_U32(prop, 0, 0x01000000); in fdt_add_pcie()
267 SET_PROP_U32(prop, 1, 0); in fdt_add_pcie()
268 SET_PROP_U32(prop, 2, 0xdf000000); in fdt_add_pcie()
270 SET_PROP_U32(prop, 3, 0); in fdt_add_pcie()
271 SET_PROP_U32(prop, 4, 0xdf000000); in fdt_add_pcie()
273 SET_PROP_U32(prop, 5, 0); in fdt_add_pcie()
274 SET_PROP_U32(prop, 6, 0x01000000); in fdt_add_pcie()
276 SET_PROP_U32(prop, 7, 0x02000000); in fdt_add_pcie()
278 SET_PROP_U32(prop, 8, 0); in fdt_add_pcie()
279 SET_PROP_U32(prop, 9, 0xa0000000); in fdt_add_pcie()
281 SET_PROP_U32(prop, 10, 0); in fdt_add_pcie()
282 SET_PROP_U32(prop, 11, 0xa0000000); in fdt_add_pcie()
284 SET_PROP_U32(prop, 12, 0); in fdt_add_pcie()
285 SET_PROP_U32(prop, 13, 0x3f000000); in fdt_add_pcie()
288 fdt_property_placeholder(fdt, "msi-map", 4 * sizeof(uint32_t), &prop); in fdt_add_pcie()
289 SET_PROP_U32(prop, 0, 0); /* RID base */ in fdt_add_pcie()
290 SET_PROP_U32(prop, 1, aplic_phandle); /* MSI parent */ in fdt_add_pcie()
291 SET_PROP_U32(prop, 2, 0); /* MSI base */ in fdt_add_pcie()
292 SET_PROP_U32(prop, 3, 0x10000); /* RID length */ in fdt_add_pcie()
293 fdt_property_u32(fdt, "msi-parent", aplic_phandle); in fdt_add_pcie()
296 fdt_property_u32(fdt, "#interrupt-cells", 1); in fdt_add_pcie()
297 fdt_property_u32(fdt, "interrupt-parent", aplic_phandle); in fdt_add_pcie()
303 fdt_property_placeholder(fdt, "interrupt-map-mask", in fdt_add_pcie()
304 4 * sizeof(uint32_t), &prop); in fdt_add_pcie()
305 SET_PROP_U32(prop, 0, 3 << 11); in fdt_add_pcie()
306 SET_PROP_U32(prop, 1, 0); in fdt_add_pcie()
307 SET_PROP_U32(prop, 2, 0); in fdt_add_pcie()
308 SET_PROP_U32(prop, 3, 7); in fdt_add_pcie()
309 fdt_property_placeholder(fdt, "interrupt-map", in fdt_add_pcie()
310 16 * 9 * sizeof(uint32_t), &prop); in fdt_add_pcie()
315 SET_PROP_U32(prop, 10 * i + 0, slot << 11); in fdt_add_pcie()
316 SET_PROP_U32(prop, 10 * i + 1, 0); in fdt_add_pcie()
317 SET_PROP_U32(prop, 10 * i + 2, 0); in fdt_add_pcie()
318 SET_PROP_U32(prop, 10 * i + 3, pin + 1); in fdt_add_pcie()
319 SET_PROP_U32(prop, 10 * i + 4, aplic_phandle); in fdt_add_pcie()
320 SET_PROP_U32(prop, 10 * i + 5, 0); in fdt_add_pcie()
321 SET_PROP_U32(prop, 10 * i + 6, 0); in fdt_add_pcie()
322 SET_PROP_U32(prop, 10 * i + 7, intr); in fdt_add_pcie()
323 SET_PROP_U32(prop, 10 * i + 8, IRQ_TYPE_LEVEL_HIGH); in fdt_add_pcie()