Lines Matching +full:0 +full:x1f
32 #define PCI_USBREV 0x60 /* USB protocol revision */
71 #define XHCI_MAX_STREAMS_LOG 0
92 #define XHCI_SCTX_0_ROUTE_SET(x) ((x) & 0xFFFFF)
93 #define XHCI_SCTX_0_ROUTE_GET(x) ((x) & 0xFFFFF)
94 #define XHCI_SCTX_0_SPEED_SET(x) (((x) & 0xF) << 20)
95 #define XHCI_SCTX_0_SPEED_GET(x) (((x) >> 20) & 0xF)
96 #define XHCI_SCTX_0_MTT_SET(x) (((x) & 0x1) << 25)
97 #define XHCI_SCTX_0_MTT_GET(x) (((x) >> 25) & 0x1)
98 #define XHCI_SCTX_0_HUB_SET(x) (((x) & 0x1) << 26)
99 #define XHCI_SCTX_0_HUB_GET(x) (((x) >> 26) & 0x1)
100 #define XHCI_SCTX_0_CTX_NUM_SET(x) (((x) & 0x1F) << 27)
101 #define XHCI_SCTX_0_CTX_NUM_GET(x) (((x) >> 27) & 0x1F)
103 #define XHCI_SCTX_1_MAX_EL_SET(x) ((x) & 0xFFFF)
104 #define XHCI_SCTX_1_MAX_EL_GET(x) ((x) & 0xFFFF)
105 #define XHCI_SCTX_1_RH_PORT_SET(x) (((x) & 0xFF) << 16)
106 #define XHCI_SCTX_1_RH_PORT_GET(x) (((x) >> 16) & 0xFF)
107 #define XHCI_SCTX_1_NUM_PORTS_SET(x) (((x) & 0xFF) << 24)
108 #define XHCI_SCTX_1_NUM_PORTS_GET(x) (((x) >> 24) & 0xFF)
110 #define XHCI_SCTX_2_TT_HUB_SID_SET(x) ((x) & 0xFF)
111 #define XHCI_SCTX_2_TT_HUB_SID_GET(x) ((x) & 0xFF)
112 #define XHCI_SCTX_2_TT_PORT_NUM_SET(x) (((x) & 0xFF) << 8)
113 #define XHCI_SCTX_2_TT_PORT_NUM_GET(x) (((x) >> 8) & 0xFF)
114 #define XHCI_SCTX_2_TT_THINK_TIME_SET(x) (((x) & 0x3) << 16)
115 #define XHCI_SCTX_2_TT_THINK_TIME_GET(x) (((x) >> 16) & 0x3)
116 #define XHCI_SCTX_2_IRQ_TARGET_SET(x) (((x) & 0x3FF) << 22)
117 #define XHCI_SCTX_2_IRQ_TARGET_GET(x) (((x) >> 22) & 0x3FF)
119 #define XHCI_SCTX_3_DEV_ADDR_SET(x) ((x) & 0xFF)
120 #define XHCI_SCTX_3_DEV_ADDR_GET(x) ((x) & 0xFF)
121 #define XHCI_SCTX_3_SLOT_STATE_SET(x) (((x) & 0x1F) << 27)
122 #define XHCI_SCTX_3_SLOT_STATE_GET(x) (((x) >> 27) & 0x1F)
131 #define XHCI_EPCTX_0_EPSTATE_SET(x) ((x) & 0x7)
132 #define XHCI_EPCTX_0_EPSTATE_GET(x) ((x) & 0x7)
133 #define XHCI_EPCTX_0_MULT_SET(x) (((x) & 0x3) << 8)
134 #define XHCI_EPCTX_0_MULT_GET(x) (((x) >> 8) & 0x3)
135 #define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) (((x) & 0x1F) << 10)
136 #define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) (((x) >> 10) & 0x1F)
137 #define XHCI_EPCTX_0_LSA_SET(x) (((x) & 0x1) << 15)
138 #define XHCI_EPCTX_0_LSA_GET(x) (((x) >> 15) & 0x1)
139 #define XHCI_EPCTX_0_IVAL_SET(x) (((x) & 0xFF) << 16)
140 #define XHCI_EPCTX_0_IVAL_GET(x) (((x) >> 16) & 0xFF)
142 #define XHCI_EPCTX_1_CERR_SET(x) (((x) & 0x3) << 1)
143 #define XHCI_EPCTX_1_CERR_GET(x) (((x) >> 1) & 0x3)
144 #define XHCI_EPCTX_1_EPTYPE_SET(x) (((x) & 0x7) << 3)
145 #define XHCI_EPCTX_1_EPTYPE_GET(x) (((x) >> 3) & 0x7)
146 #define XHCI_EPCTX_1_HID_SET(x) (((x) & 0x1) << 7)
147 #define XHCI_EPCTX_1_HID_GET(x) (((x) >> 7) & 0x1)
148 #define XHCI_EPCTX_1_MAXB_SET(x) (((x) & 0xFF) << 8)
149 #define XHCI_EPCTX_1_MAXB_GET(x) (((x) >> 8) & 0xFF)
150 #define XHCI_EPCTX_1_MAXP_SIZE_SET(x) (((x) & 0xFFFF) << 16)
151 #define XHCI_EPCTX_1_MAXP_SIZE_GET(x) (((x) >> 16) & 0xFFFF)
153 #define XHCI_EPCTX_2_DCS_SET(x) ((x) & 0x1)
154 #define XHCI_EPCTX_2_DCS_GET(x) ((x) & 0x1)
155 #define XHCI_EPCTX_2_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U
157 #define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) ((x) & 0xFFFF)
158 #define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) ((x) & 0xFFFF)
159 #define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) (((x) & 0xFFFF) << 16)
160 #define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) (((x) >> 16) & 0xFFFF)
167 #define XHCI_INCTX_NON_CTRL_MASK 0xFFFFFFFCU
199 #define XHCI_SCTX_0_DCS_GET(x) ((x) & 0x1)
200 #define XHCI_SCTX_0_DCS_SET(x) ((x) & 0x1)
201 #define XHCI_SCTX_0_SCT_SET(x) (((x) & 0x7) << 1)
202 #define XHCI_SCTX_0_SCT_GET(x) (((x) >> 1) & 0x7)
203 #define XHCI_SCTX_0_SCT_SEC_TR_RING 0x0
204 #define XHCI_SCTX_0_SCT_PRIM_TR_RING 0x1
205 #define XHCI_SCTX_0_SCT_PRIM_SSA_8 0x2
206 #define XHCI_SCTX_0_SCT_PRIM_SSA_16 0x3
207 #define XHCI_SCTX_0_SCT_PRIM_SSA_32 0x4
208 #define XHCI_SCTX_0_SCT_PRIM_SSA_64 0x5
209 #define XHCI_SCTX_0_SCT_PRIM_SSA_128 0x6
210 #define XHCI_SCTX_0_SCT_PRIM_SSA_256 0x7
211 #define XHCI_SCTX_0_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U
218 #define XHCI_TRB_0_DIR_IN_MASK (0x80ULL << 0)
219 #define XHCI_TRB_0_WLENGTH_MASK (0xFFFFULL << 48)
221 #define XHCI_TRB_2_ERROR_GET(x) (((x) >> 24) & 0xFF)
222 #define XHCI_TRB_2_ERROR_SET(x) (((x) & 0xFF) << 24)
223 #define XHCI_TRB_2_TDSZ_GET(x) (((x) >> 17) & 0x1F)
224 #define XHCI_TRB_2_TDSZ_SET(x) (((x) & 0x1F) << 17)
225 #define XHCI_TRB_2_REM_GET(x) ((x) & 0xFFFFFF)
226 #define XHCI_TRB_2_REM_SET(x) ((x) & 0xFFFFFF)
227 #define XHCI_TRB_2_BYTES_GET(x) ((x) & 0x1FFFF)
228 #define XHCI_TRB_2_BYTES_SET(x) ((x) & 0x1FFFF)
229 #define XHCI_TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF)
230 #define XHCI_TRB_2_IRQ_SET(x) (((x) & 0x3FF) << 22)
231 #define XHCI_TRB_2_STREAM_GET(x) (((x) >> 16) & 0xFFFF)
232 #define XHCI_TRB_2_STREAM_SET(x) (((x) & 0xFFFF) << 16)
235 #define XHCI_TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F)
236 #define XHCI_TRB_3_TYPE_SET(x) (((x) & 0x3F) << 10)
237 #define XHCI_TRB_3_CYCLE_BIT (1U << 0)
253 #define XHCI_TRB_3_TRT_NONE (0U << 16)
257 #define XHCI_TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xF)
258 #define XHCI_TRB_3_TLBPC_SET(x) (((x) & 0xF) << 16)
259 #define XHCI_TRB_3_EP_GET(x) (((x) >> 16) & 0x1F)
260 #define XHCI_TRB_3_EP_SET(x) (((x) & 0x1F) << 16)
261 #define XHCI_TRB_3_FRID_GET(x) (((x) >> 20) & 0x7FF)
262 #define XHCI_TRB_3_FRID_SET(x) (((x) & 0x7FF) << 20)
265 #define XHCI_TRB_3_SLOT_GET(x) (((x) >> 24) & 0xFF)
266 #define XHCI_TRB_3_SLOT_SET(x) (((x) & 0xFF) << 24)
269 #define XHCI_TRB_TYPE_RESERVED 0x00
270 #define XHCI_TRB_TYPE_NORMAL 0x01
271 #define XHCI_TRB_TYPE_SETUP_STAGE 0x02
272 #define XHCI_TRB_TYPE_DATA_STAGE 0x03
273 #define XHCI_TRB_TYPE_STATUS_STAGE 0x04
274 #define XHCI_TRB_TYPE_ISOCH 0x05
275 #define XHCI_TRB_TYPE_LINK 0x06
276 #define XHCI_TRB_TYPE_EVENT_DATA 0x07
277 #define XHCI_TRB_TYPE_NOOP 0x08
278 #define XHCI_TRB_TYPE_ENABLE_SLOT 0x09
279 #define XHCI_TRB_TYPE_DISABLE_SLOT 0x0A
280 #define XHCI_TRB_TYPE_ADDRESS_DEVICE 0x0B
281 #define XHCI_TRB_TYPE_CONFIGURE_EP 0x0C
282 #define XHCI_TRB_TYPE_EVALUATE_CTX 0x0D
283 #define XHCI_TRB_TYPE_RESET_EP 0x0E
284 #define XHCI_TRB_TYPE_STOP_EP 0x0F
285 #define XHCI_TRB_TYPE_SET_TR_DEQUEUE 0x10
286 #define XHCI_TRB_TYPE_RESET_DEVICE 0x11
287 #define XHCI_TRB_TYPE_FORCE_EVENT 0x12
288 #define XHCI_TRB_TYPE_NEGOTIATE_BW 0x13
289 #define XHCI_TRB_TYPE_SET_LATENCY_TOL 0x14
290 #define XHCI_TRB_TYPE_GET_PORT_BW 0x15
291 #define XHCI_TRB_TYPE_FORCE_HEADER 0x16
292 #define XHCI_TRB_TYPE_NOOP_CMD 0x17
295 #define XHCI_TRB_EVENT_TRANSFER 0x20
296 #define XHCI_TRB_EVENT_CMD_COMPLETE 0x21
297 #define XHCI_TRB_EVENT_PORT_STS_CHANGE 0x22
298 #define XHCI_TRB_EVENT_BW_REQUEST 0x23
299 #define XHCI_TRB_EVENT_DOORBELL 0x24
300 #define XHCI_TRB_EVENT_HOST_CTRL 0x25
301 #define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26
302 #define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27
305 #define XHCI_TRB_ERROR_INVALID 0x00
306 #define XHCI_TRB_ERROR_SUCCESS 0x01
307 #define XHCI_TRB_ERROR_DATA_BUF 0x02
308 #define XHCI_TRB_ERROR_BABBLE 0x03
309 #define XHCI_TRB_ERROR_XACT 0x04
310 #define XHCI_TRB_ERROR_TRB 0x05
311 #define XHCI_TRB_ERROR_STALL 0x06
312 #define XHCI_TRB_ERROR_RESOURCE 0x07
313 #define XHCI_TRB_ERROR_BANDWIDTH 0x08
314 #define XHCI_TRB_ERROR_NO_SLOTS 0x09
315 #define XHCI_TRB_ERROR_STREAM_TYPE 0x0A
316 #define XHCI_TRB_ERROR_SLOT_NOT_ON 0x0B
317 #define XHCI_TRB_ERROR_ENDP_NOT_ON 0x0C
318 #define XHCI_TRB_ERROR_SHORT_PKT 0x0D
319 #define XHCI_TRB_ERROR_RING_UNDERRUN 0x0E
320 #define XHCI_TRB_ERROR_RING_OVERRUN 0x0F
321 #define XHCI_TRB_ERROR_VF_RING_FULL 0x10
322 #define XHCI_TRB_ERROR_PARAMETER 0x11
323 #define XHCI_TRB_ERROR_BW_OVERRUN 0x12
324 #define XHCI_TRB_ERROR_CONTEXT_STATE 0x13
325 #define XHCI_TRB_ERROR_NO_PING_RESP 0x14
326 #define XHCI_TRB_ERROR_EV_RING_FULL 0x15
327 #define XHCI_TRB_ERROR_INCOMPAT_DEV 0x16
328 #define XHCI_TRB_ERROR_MISSED_SERVICE 0x17
329 #define XHCI_TRB_ERROR_CMD_RING_STOP 0x18
330 #define XHCI_TRB_ERROR_CMD_ABORTED 0x19
331 #define XHCI_TRB_ERROR_STOPPED 0x1A
332 #define XHCI_TRB_ERROR_LENGTH 0x1B
333 #define XHCI_TRB_ERROR_BAD_MELAT 0x1D
334 #define XHCI_TRB_ERROR_ISOC_OVERRUN 0x1F
335 #define XHCI_TRB_ERROR_EVENT_LOST 0x20
336 #define XHCI_TRB_ERROR_UNDEFINED 0x21
337 #define XHCI_TRB_ERROR_INVALID_SID 0x22
338 #define XHCI_TRB_ERROR_SEC_BW 0x23
339 #define XHCI_TRB_ERROR_SPLIT_XACT 0x24