357 	evtrb->qwTrb0 = port << 24;  in pci_xhci_set_evtrb()
612 			*guestaddr = curtrb->qwTrb0 & ~0xFUL;  in pci_xhci_trb_next()
614 		next = XHCI_GADDR(sc, curtrb->qwTrb0 & ~0xFUL);  in pci_xhci_trb_next()
756 	         evtrb->qwTrb0, evtrb->dwTrb2, evtrb->dwTrb3));  in pci_xhci_insert_event()
782 			errev.qwTrb0 = 0;  in pci_xhci_insert_event()
944 	input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL);  in pci_xhci_cmd_address_device()
1094 	input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL);  in pci_xhci_cmd_config_ep()
1257 	         (trb->qwTrb0 & ~0xF),  (uint32_t)((trb->qwTrb0 >> 1) & 0x7),  in pci_xhci_cmd_set_tr()
1258 	         (uint32_t)(trb->qwTrb0 & 0x1)));  in pci_xhci_cmd_set_tr()
1294 			devep->ep_sctx[streamid].qwSctx0 = trb->qwTrb0;  in pci_xhci_cmd_set_tr()
1296 			    trb->qwTrb0 & ~0xF;  in pci_xhci_cmd_set_tr()
1298 			    XHCI_EPCTX_2_DCS_GET(trb->qwTrb0);  in pci_xhci_cmd_set_tr()
1305 		ep_ctx->qwEpCtx2 = trb->qwTrb0 & ~0xFUL;  in pci_xhci_cmd_set_tr()
1307 		devep->ep_ccs = trb->qwTrb0 & 0x1;  in pci_xhci_cmd_set_tr()
1329 	input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL);  in pci_xhci_cmd_eval_ctx()
1428 		        type, trb->qwTrb0, trb->dwTrb2, trb->dwTrb3,  in pci_xhci_complete_commands()
1517 			evtrb.qwTrb0 = crcr;  in pci_xhci_complete_commands()
1568 	         trb->qwTrb0, trb->dwTrb2, trb->dwTrb3));  in pci_xhci_dump_trb()
1600 		evtrb.qwTrb0 = (uint64_t)xfer->data[i].hci_data;  in pci_xhci_xfer_complete()
1601 		trb = XHCI_GADDR(sc, evtrb.qwTrb0);  in pci_xhci_xfer_complete()
1607 		     XHCI_TRB_3_TYPE_GET(trbflags), evtrb.qwTrb0,  in pci_xhci_xfer_complete()
1642 			evtrb.qwTrb0 = trb->qwTrb0;  in pci_xhci_xfer_complete()
1812 			val = trb->qwTrb0;  in pci_xhci_handle_transfer()
1837 			         &trb->qwTrb0 : XHCI_GADDR(sc, trb->qwTrb0)),  in pci_xhci_handle_transfer()