823 	uint32_t	cmderr;  in pci_xhci_cmd_enable_slot()  local
826 	cmderr = XHCI_TRB_ERROR_NO_SLOTS;  in pci_xhci_cmd_enable_slot()
833 				cmderr = XHCI_TRB_ERROR_SUCCESS;  in pci_xhci_cmd_enable_slot()
840 		cmderr != XHCI_TRB_ERROR_SUCCESS, *slot));  in pci_xhci_cmd_enable_slot()
842 	return (cmderr);  in pci_xhci_cmd_enable_slot()
849 	uint32_t cmderr;  in pci_xhci_cmd_disable_slot()  local
854 		cmderr = XHCI_TRB_ERROR_NO_SLOTS;  in pci_xhci_cmd_disable_slot()
858 	cmderr = pci_xhci_validate_slot(slot);  in pci_xhci_cmd_disable_slot()
859 	if (cmderr != XHCI_TRB_ERROR_SUCCESS)  in pci_xhci_cmd_disable_slot()
865 			cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON;  in pci_xhci_cmd_disable_slot()
871 		cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON;  in pci_xhci_cmd_disable_slot()
874 	return (cmderr);  in pci_xhci_cmd_disable_slot()
883 	uint32_t	cmderr;  in pci_xhci_cmd_reset_device()  local
887 		cmderr = XHCI_TRB_ERROR_NO_SLOTS;  in pci_xhci_cmd_reset_device()
893 	cmderr = pci_xhci_validate_slot(slot);  in pci_xhci_cmd_reset_device()
894 	if (cmderr != XHCI_TRB_ERROR_SUCCESS)  in pci_xhci_cmd_reset_device()
899 		cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON;  in pci_xhci_cmd_reset_device()
906 			cmderr = XHCI_TRB_ERROR_PARAMETER;  in pci_xhci_cmd_reset_device()
930 	return (cmderr);  in pci_xhci_cmd_reset_device()
942 	uint32_t		cmderr;  in pci_xhci_cmd_address_device()  local
961 		cmderr = XHCI_TRB_ERROR_TRB;  in pci_xhci_cmd_address_device()
965 	cmderr = pci_xhci_validate_slot(slot);  in pci_xhci_cmd_address_device()
966 	if (cmderr != XHCI_TRB_ERROR_SUCCESS)  in pci_xhci_cmd_address_device()
972 		cmderr = XHCI_TRB_ERROR_PARAMETER;  in pci_xhci_cmd_address_device()
989 		cmderr = XHCI_TRB_ERROR_ENDP_NOT_ON;  in pci_xhci_cmd_address_device()
1017 	return (cmderr);  in pci_xhci_cmd_address_device()
1028 	uint32_t	cmderr;  in pci_xhci_cmd_config_ep()  local
1033 	cmderr = pci_xhci_validate_slot(slot);  in pci_xhci_cmd_config_ep()
1034 	if (cmderr != XHCI_TRB_ERROR_SUCCESS)  in pci_xhci_cmd_config_ep()
1051 			cmderr = XHCI_TRB_ERROR_PARAMETER;  in pci_xhci_cmd_config_ep()
1068 		cmderr = XHCI_TRB_ERROR_SUCCESS;  in pci_xhci_cmd_config_ep()
1076 		cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON;  in pci_xhci_cmd_config_ep()
1140 	return (cmderr);  in pci_xhci_cmd_config_ep()
1151 	uint32_t	cmderr, epid;  in pci_xhci_cmd_reset_ep()  local
1158 	cmderr = pci_xhci_validate_slot(slot);  in pci_xhci_cmd_reset_ep()
1159 	if (cmderr != XHCI_TRB_ERROR_SUCCESS)  in pci_xhci_cmd_reset_ep()
1174 		cmderr = XHCI_TRB_ERROR_TRB;  in pci_xhci_cmd_reset_ep()
1199 		cmderr = XHCI_TRB_ERROR_ENDP_NOT_ON;  in pci_xhci_cmd_reset_ep()
1204 	return (cmderr);  in pci_xhci_cmd_reset_ep()
1246 	uint32_t	cmderr, epid;  in pci_xhci_cmd_set_tr()  local
1249 	cmderr = pci_xhci_validate_slot(slot);  in pci_xhci_cmd_set_tr()
1250 	if (cmderr != XHCI_TRB_ERROR_SUCCESS)  in pci_xhci_cmd_set_tr()
1267 		cmderr = XHCI_TRB_ERROR_TRB;  in pci_xhci_cmd_set_tr()
1284 		cmderr = XHCI_TRB_ERROR_CONTEXT_STATE;  in pci_xhci_cmd_set_tr()
1290 		cmderr = pci_xhci_find_stream(sc, ep_ctx, devep, streamid);  in pci_xhci_cmd_set_tr()
1291 		if (cmderr == XHCI_TRB_ERROR_SUCCESS) {  in pci_xhci_cmd_set_tr()
1316 	return (cmderr);  in pci_xhci_cmd_set_tr()
1327 	uint32_t cmderr;  in pci_xhci_cmd_eval_ctx()  local
1346 		cmderr = XHCI_TRB_ERROR_TRB;  in pci_xhci_cmd_eval_ctx()
1350 	cmderr = pci_xhci_validate_slot(slot);  in pci_xhci_cmd_eval_ctx()
1351 	if (cmderr != XHCI_TRB_ERROR_SUCCESS)  in pci_xhci_cmd_eval_ctx()
1357 		cmderr = XHCI_TRB_ERROR_PARAMETER;  in pci_xhci_cmd_eval_ctx()
1395 	return (cmderr);  in pci_xhci_cmd_eval_ctx()
1407 	uint32_t	cmderr;  in pci_xhci_complete_commands()  local
1431 		cmderr = XHCI_TRB_ERROR_SUCCESS;  in pci_xhci_complete_commands()
1444 			cmderr = pci_xhci_cmd_enable_slot(sc, &slot);  in pci_xhci_complete_commands()
1449 			cmderr = pci_xhci_cmd_disable_slot(sc, slot);  in pci_xhci_complete_commands()
1454 			cmderr = pci_xhci_cmd_address_device(sc, slot, trb);  in pci_xhci_complete_commands()
1459 			cmderr = pci_xhci_cmd_config_ep(sc, slot, trb);  in pci_xhci_complete_commands()
1464 			cmderr = pci_xhci_cmd_eval_ctx(sc, slot, trb);  in pci_xhci_complete_commands()
1470 			cmderr = pci_xhci_cmd_reset_ep(sc, slot, trb);  in pci_xhci_complete_commands()
1476 			cmderr = pci_xhci_cmd_reset_ep(sc, slot, trb);  in pci_xhci_complete_commands()
1481 			cmderr = pci_xhci_cmd_set_tr(sc, slot, trb);  in pci_xhci_complete_commands()
1486 			cmderr = pci_xhci_cmd_reset_device(sc, slot);  in pci_xhci_complete_commands()
1518 			evtrb.dwTrb2 |= XHCI_TRB_2_ERROR_SET(cmderr);  in pci_xhci_complete_commands()
1521 			        type, cmderr));  in pci_xhci_complete_commands()