Lines Matching full:pi
159 static void pci_lintr_route(struct pci_devinst *pi);
160 static void pci_lintr_update(struct pci_devinst *pi);
167 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes) in CFGWRITE() argument
171 pci_set_cfgdata8(pi, coff, val); in CFGWRITE()
173 pci_set_cfgdata16(pi, coff, val); in CFGWRITE()
175 pci_set_cfgdata32(pi, coff, val); in CFGWRITE()
179 CFGREAD(struct pci_devinst *pi, int coff, int bytes) in CFGREAD() argument
183 return (pci_get_cfgdata8(pi, coff)); in CFGREAD()
185 return (pci_get_cfgdata16(pi, coff)); in CFGREAD()
187 return (pci_get_cfgdata32(pi, coff)); in CFGREAD()
403 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) in pci_valid_pba_offset() argument
406 if (offset < pi->pi_msix.pba_offset) in pci_valid_pba_offset()
409 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { in pci_valid_pba_offset()
417 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, in pci_emul_msix_twrite() argument
432 if (tab_index >= pi->pi_msix.table_count) in pci_emul_msix_twrite()
441 dest = (char *)(pi->pi_msix.table + tab_index); in pci_emul_msix_twrite()
453 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) in pci_emul_msix_tread() argument
477 if (tab_index < pi->pi_msix.table_count) { in pci_emul_msix_tread()
479 dest = (char *)(pi->pi_msix.table + tab_index); in pci_emul_msix_tread()
488 } else if (pci_valid_pba_offset(pi, offset)) { in pci_emul_msix_tread()
497 pci_msix_table_bar(struct pci_devinst *pi) in pci_msix_table_bar() argument
500 if (pi->pi_msix.table != NULL) in pci_msix_table_bar()
501 return (pi->pi_msix.table_bar); in pci_msix_table_bar()
507 pci_msix_pba_bar(struct pci_devinst *pi) in pci_msix_pba_bar() argument
510 if (pi->pi_msix.table != NULL) in pci_msix_pba_bar()
511 return (pi->pi_msix.pba_bar); in pci_msix_pba_bar()
637 modify_bar_registration(struct pci_devinst *pi, int idx, int registration) in modify_bar_registration() argument
643 pe = pi->pi_d; in modify_bar_registration()
644 type = pi->pi_bar[idx].type; in modify_bar_registration()
652 iop.name = pi->pi_name; in modify_bar_registration()
653 iop.port = pi->pi_bar[idx].addr; in modify_bar_registration()
654 iop.size = pi->pi_bar[idx].size; in modify_bar_registration()
658 iop.arg = pi; in modify_bar_registration()
666 mr.name = pi->pi_name; in modify_bar_registration()
667 mr.base = pi->pi_bar[idx].addr; in modify_bar_registration()
668 mr.size = pi->pi_bar[idx].size; in modify_bar_registration()
672 mr.arg1 = pi; in modify_bar_registration()
686 mr.name = pi->pi_name; in modify_bar_registration()
687 mr.base = pi->pi_bar[idx].addr; in modify_bar_registration()
688 mr.size = pi->pi_bar[idx].size; in modify_bar_registration()
692 mr.arg1 = pi; in modify_bar_registration()
709 (*pe->pe_baraddr)(pi, idx, registration, pi->pi_bar[idx].addr); in modify_bar_registration()
713 unregister_bar(struct pci_devinst *pi, int idx) in unregister_bar() argument
716 modify_bar_registration(pi, idx, 0); in unregister_bar()
720 register_bar(struct pci_devinst *pi, int idx) in register_bar() argument
723 modify_bar_registration(pi, idx, 1); in register_bar()
728 romen(struct pci_devinst *pi) in romen() argument
730 return (pi->pi_bar[PCI_ROM_IDX].lobits & PCIM_BIOS_ENABLE) == in romen()
736 porten(struct pci_devinst *pi) in porten() argument
740 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); in porten()
747 memen(struct pci_devinst *pi) in memen() argument
751 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); in memen()
763 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) in update_bar_address() argument
767 if (pi->pi_bar[idx].type == PCIBAR_IO) in update_bar_address()
768 decode = porten(pi); in update_bar_address()
770 decode = memen(pi); in update_bar_address()
773 unregister_bar(pi, idx); in update_bar_address()
778 pi->pi_bar[idx].addr = addr; in update_bar_address()
781 pi->pi_bar[idx].addr &= ~0xffffffffUL; in update_bar_address()
782 pi->pi_bar[idx].addr |= addr; in update_bar_address()
785 pi->pi_bar[idx].addr &= 0xffffffff; in update_bar_address()
786 pi->pi_bar[idx].addr |= addr; in update_bar_address()
793 register_bar(pi, idx); in update_bar_address()
1046 pci_emul_add_boot_device(struct pci_devinst *pi, int bootindex) in pci_emul_add_boot_device() argument
1052 errx(4, "Invalid bootindex %d for %s", bootindex, pi->pi_name); in pci_emul_add_boot_device()
1060 new_device->pdi = pi; in pci_emul_add_boot_device()
1068 bootindex, pi->pi_name, device->pdi->pi_name); in pci_emul_add_boot_device()
1086 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) in pci_emul_add_capability() argument
1095 sts = pci_get_cfgdata16(pi, PCIR_STATUS); in pci_emul_add_capability()
1099 capoff = pi->pi_capend + 1; in pci_emul_add_capability()
1107 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); in pci_emul_add_capability()
1108 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); in pci_emul_add_capability()
1110 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff); in pci_emul_add_capability()
1114 pci_set_cfgdata8(pi, capoff + i, capdata[i]); in pci_emul_add_capability()
1117 pci_set_cfgdata8(pi, capoff + 1, 0); in pci_emul_add_capability()
1119 pi->pi_prevcap = capoff; in pci_emul_add_capability()
1120 pi->pi_capend = capoff + reallen - 1; in pci_emul_add_capability()
1192 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) in pci_emul_add_msicap() argument
1198 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); in pci_emul_add_msicap()
1228 pci_msix_table_init(struct pci_devinst *pi, int table_entries) in pci_msix_table_init() argument
1236 pi->pi_msix.table = calloc(1, table_size); in pci_msix_table_init()
1240 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; in pci_msix_table_init()
1244 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) in pci_emul_add_msixcap() argument
1257 pi->pi_msix.table_bar = barnum; in pci_emul_add_msixcap()
1258 pi->pi_msix.pba_bar = barnum; in pci_emul_add_msixcap()
1259 pi->pi_msix.table_offset = 0; in pci_emul_add_msixcap()
1260 pi->pi_msix.table_count = msgnum; in pci_emul_add_msixcap()
1261 pi->pi_msix.pba_offset = tab_size; in pci_emul_add_msixcap()
1262 pi->pi_msix.pba_size = PBA_SIZE(msgnum); in pci_emul_add_msixcap()
1264 pci_msix_table_init(pi, msgnum); in pci_emul_add_msixcap()
1269 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, in pci_emul_add_msixcap()
1270 tab_size + pi->pi_msix.pba_size); in pci_emul_add_msixcap()
1272 return (pci_emul_add_capability(pi, (u_char *)&msixcap, in pci_emul_add_msixcap()
1277 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, in msixcap_cfgwrite() argument
1287 msgctrl = pci_get_cfgdata16(pi, offset); in msixcap_cfgwrite()
1292 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; in msixcap_cfgwrite()
1293 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; in msixcap_cfgwrite()
1294 pci_lintr_update(pi); in msixcap_cfgwrite()
1297 CFGWRITE(pi, offset, val, bytes); in msixcap_cfgwrite()
1301 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, in msicap_cfgwrite() argument
1313 msgctrl = pci_get_cfgdata16(pi, offset); in msicap_cfgwrite()
1318 CFGWRITE(pi, offset, val, bytes); in msicap_cfgwrite()
1320 msgctrl = pci_get_cfgdata16(pi, capoff + 2); in msicap_cfgwrite()
1321 addrlo = pci_get_cfgdata32(pi, capoff + 4); in msicap_cfgwrite()
1323 msgdata = pci_get_cfgdata16(pi, capoff + 12); in msicap_cfgwrite()
1325 msgdata = pci_get_cfgdata16(pi, capoff + 8); in msicap_cfgwrite()
1328 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; in msicap_cfgwrite()
1329 if (pi->pi_msi.enabled) { in msicap_cfgwrite()
1330 pi->pi_msi.addr = addrlo; in msicap_cfgwrite()
1331 pi->pi_msi.msg_data = msgdata; in msicap_cfgwrite()
1332 pi->pi_msi.maxmsgnum = 1 << (mme >> 4); in msicap_cfgwrite()
1334 pi->pi_msi.maxmsgnum = 0; in msicap_cfgwrite()
1336 pci_lintr_update(pi); in msicap_cfgwrite()
1340 pciecap_cfgwrite(struct pci_devinst *pi, int capoff __unused, int offset, in pciecap_cfgwrite() argument
1345 CFGWRITE(pi, offset, val, bytes); in pciecap_cfgwrite()
1350 pci_emul_add_pciecap(struct pci_devinst *pi, int type) in pci_emul_add_pciecap() argument
1363 if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0)) in pci_emul_add_pciecap()
1373 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); in pci_emul_add_pciecap()
1383 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val, in pci_emul_capwrite() argument
1396 nextoff = pci_get_cfgdata8(pi, capoff + 1); in pci_emul_capwrite()
1405 capid = pci_get_cfgdata8(pi, capoff); in pci_emul_capwrite()
1425 msicap_cfgwrite(pi, capoff, offset, bytes, val); in pci_emul_capwrite()
1428 msixcap_cfgwrite(pi, capoff, offset, bytes, val); in pci_emul_capwrite()
1431 pciecap_cfgwrite(pi, capoff, offset, bytes, val); in pci_emul_capwrite()
1439 pci_emul_iscap(struct pci_devinst *pi, int offset) in pci_emul_iscap() argument
1443 sts = pci_get_cfgdata16(pi, PCIR_STATUS); in pci_emul_iscap()
1445 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend) in pci_emul_iscap()
1751 struct pci_devinst *pi; in pci_bus_write_dsdt() local
1887 pi = si->si_funcs[func].fi_devi; in pci_bus_write_dsdt()
1888 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL) in pci_bus_write_dsdt()
1889 pi->pi_d->pe_write_dsdt(pi); in pci_bus_write_dsdt()
1927 pci_msi_enabled(struct pci_devinst *pi) in pci_msi_enabled() argument
1929 return (pi->pi_msi.enabled); in pci_msi_enabled()
1933 pci_msi_maxmsgnum(struct pci_devinst *pi) in pci_msi_maxmsgnum() argument
1935 if (pi->pi_msi.enabled) in pci_msi_maxmsgnum()
1936 return (pi->pi_msi.maxmsgnum); in pci_msi_maxmsgnum()
1942 pci_msix_enabled(struct pci_devinst *pi) in pci_msix_enabled() argument
1945 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); in pci_msix_enabled()
1949 pci_generate_msix(struct pci_devinst *pi, int index) in pci_generate_msix() argument
1953 if (!pci_msix_enabled(pi)) in pci_generate_msix()
1956 if (pi->pi_msix.function_mask) in pci_generate_msix()
1959 if (index >= pi->pi_msix.table_count) in pci_generate_msix()
1962 mte = &pi->pi_msix.table[index]; in pci_generate_msix()
1965 vm_raise_msi(pi->pi_vmctx, mte->addr, mte->msg_data, in pci_generate_msix()
1966 pi->pi_bus, pi->pi_slot, pi->pi_func); in pci_generate_msix()
1971 pci_generate_msi(struct pci_devinst *pi, int index) in pci_generate_msi() argument
1974 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) { in pci_generate_msi()
1975 vm_raise_msi(pi->pi_vmctx, pi->pi_msi.addr, in pci_generate_msi()
1976 pi->pi_msi.msg_data + index, in pci_generate_msi()
1977 pi->pi_bus, pi->pi_slot, pi->pi_func); in pci_generate_msi()
1982 pci_lintr_permitted(struct pci_devinst *pi) in pci_lintr_permitted() argument
1986 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); in pci_lintr_permitted()
1987 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled || in pci_lintr_permitted()
1992 pci_lintr_request(struct pci_devinst *pi) in pci_lintr_request() argument
1998 bi = pci_businfo[pi->pi_bus]; in pci_lintr_request()
2005 si = &bi->slotinfo[pi->pi_slot]; in pci_lintr_request()
2016 pi->pi_lintr.pin = bestpin + 1; in pci_lintr_request()
2017 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1); in pci_lintr_request()
2021 pci_lintr_route(struct pci_devinst *pi) in pci_lintr_route() argument
2027 if (pi->pi_lintr.pin == 0) in pci_lintr_route()
2030 bi = pci_businfo[pi->pi_bus]; in pci_lintr_route()
2032 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1]; in pci_lintr_route()
2034 pci_irq_route(pi, irq); in pci_lintr_route()
2035 pi->pi_lintr.irq = *irq; in pci_lintr_route()
2036 pci_set_cfgdata8(pi, PCIR_INTLINE, pci_irq_intline(irq)); in pci_lintr_route()
2040 pci_lintr_assert(struct pci_devinst *pi) in pci_lintr_assert() argument
2043 assert(pi->pi_lintr.pin > 0); in pci_lintr_assert()
2045 pthread_mutex_lock(&pi->pi_lintr.lock); in pci_lintr_assert()
2046 if (pi->pi_lintr.state == IDLE) { in pci_lintr_assert()
2047 if (pci_lintr_permitted(pi)) { in pci_lintr_assert()
2048 pi->pi_lintr.state = ASSERTED; in pci_lintr_assert()
2049 pci_irq_assert(pi); in pci_lintr_assert()
2051 pi->pi_lintr.state = PENDING; in pci_lintr_assert()
2053 pthread_mutex_unlock(&pi->pi_lintr.lock); in pci_lintr_assert()
2057 pci_lintr_deassert(struct pci_devinst *pi) in pci_lintr_deassert() argument
2060 assert(pi->pi_lintr.pin > 0); in pci_lintr_deassert()
2062 pthread_mutex_lock(&pi->pi_lintr.lock); in pci_lintr_deassert()
2063 if (pi->pi_lintr.state == ASSERTED) { in pci_lintr_deassert()
2064 pi->pi_lintr.state = IDLE; in pci_lintr_deassert()
2065 pci_irq_deassert(pi); in pci_lintr_deassert()
2066 } else if (pi->pi_lintr.state == PENDING) in pci_lintr_deassert()
2067 pi->pi_lintr.state = IDLE; in pci_lintr_deassert()
2068 pthread_mutex_unlock(&pi->pi_lintr.lock); in pci_lintr_deassert()
2072 pci_lintr_update(struct pci_devinst *pi) in pci_lintr_update() argument
2075 pthread_mutex_lock(&pi->pi_lintr.lock); in pci_lintr_update()
2076 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) { in pci_lintr_update()
2077 pci_irq_deassert(pi); in pci_lintr_update()
2078 pi->pi_lintr.state = PENDING; in pci_lintr_update()
2079 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) { in pci_lintr_update()
2080 pi->pi_lintr.state = ASSERTED; in pci_lintr_update()
2081 pci_irq_assert(pi); in pci_lintr_update()
2083 pthread_mutex_unlock(&pi->pi_lintr.lock); in pci_lintr_update()
2183 pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old) in pci_emul_cmd_changed() argument
2188 new = pci_get_cfgdata16(pi, PCIR_COMMAND); in pci_emul_cmd_changed()
2196 switch (pi->pi_bar[i].type) { in pci_emul_cmd_changed()
2204 register_bar(pi, i); in pci_emul_cmd_changed()
2206 unregister_bar(pi, i); in pci_emul_cmd_changed()
2211 if (!romen(pi)) in pci_emul_cmd_changed()
2219 register_bar(pi, i); in pci_emul_cmd_changed()
2221 unregister_bar(pi, i); in pci_emul_cmd_changed()
2233 pci_lintr_update(pi); in pci_emul_cmd_changed()
2237 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes) in pci_emul_cmdsts_write() argument
2242 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ in pci_emul_cmdsts_write()
2254 old = CFGREAD(pi, coff, bytes); in pci_emul_cmdsts_write()
2257 CFGWRITE(pi, coff, new, bytes); /* update config */ in pci_emul_cmdsts_write()
2259 pci_emul_cmd_changed(pi, cmd); in pci_emul_cmdsts_write()
2268 struct pci_devinst *pi; in pci_cfgrw() local
2275 pi = si->si_funcs[func].fi_devi; in pci_cfgrw()
2277 pi = NULL; in pci_cfgrw()
2283 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) || in pci_cfgrw()
2309 pe = pi->pi_d; in pci_cfgrw()
2317 needcfg = pe->pe_cfgread(pi, coff, bytes, valp); in pci_cfgrw()
2323 *valp = CFGREAD(pi, coff, bytes); in pci_cfgrw()
2329 (*pe->pe_cfgwrite)(pi, coff, bytes, *valp) == 0) in pci_cfgrw()
2352 mask = ~(pi->pi_bar[idx].size - 1); in pci_cfgrw()
2353 switch (pi->pi_bar[idx].type) { in pci_cfgrw()
2355 pi->pi_bar[idx].addr = bar = 0; in pci_cfgrw()
2362 bar = addr | pi->pi_bar[idx].lobits; in pci_cfgrw()
2366 if (addr != pi->pi_bar[idx].addr) { in pci_cfgrw()
2367 update_bar_address(pi, addr, idx, in pci_cfgrw()
2373 bar |= pi->pi_bar[idx].lobits; in pci_cfgrw()
2374 if (addr != pi->pi_bar[idx].addr) { in pci_cfgrw()
2375 update_bar_address(pi, addr, idx, in pci_cfgrw()
2381 bar |= pi->pi_bar[idx].lobits; in pci_cfgrw()
2382 if (addr != (uint32_t)pi->pi_bar[idx].addr) { in pci_cfgrw()
2383 update_bar_address(pi, addr, idx, in pci_cfgrw()
2388 mask = ~(pi->pi_bar[idx - 1].size - 1); in pci_cfgrw()
2391 if (bar != pi->pi_bar[idx - 1].addr >> 32) { in pci_cfgrw()
2392 update_bar_address(pi, addr, idx - 1, in pci_cfgrw()
2398 if (memen(pi) && romen(pi)) { in pci_cfgrw()
2399 unregister_bar(pi, idx); in pci_cfgrw()
2401 pi->pi_bar[idx].addr = addr; in pci_cfgrw()
2402 pi->pi_bar[idx].lobits = *valp & in pci_cfgrw()
2405 if (memen(pi) && romen(pi)) { in pci_cfgrw()
2406 register_bar(pi, idx); in pci_cfgrw()
2408 bar |= pi->pi_bar[idx].lobits; in pci_cfgrw()
2413 pci_set_cfgdata32(pi, coff, bar); in pci_cfgrw()
2415 } else if (pci_emul_iscap(pi, coff)) { in pci_cfgrw()
2416 pci_emul_capwrite(pi, coff, bytes, *valp, 0, 0); in pci_cfgrw()
2418 pci_emul_cmdsts_write(pi, coff, *valp, bytes); in pci_cfgrw()
2420 CFGWRITE(pi, coff, *valp, bytes); in pci_cfgrw()
2490 struct pci_devinst *pi; in pci_snapshot_pci_dev() local
2494 pi = meta->dev_data; in pci_snapshot_pci_dev()
2496 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.enabled, meta, ret, done); in pci_snapshot_pci_dev()
2497 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.addr, meta, ret, done); in pci_snapshot_pci_dev()
2498 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.msg_data, meta, ret, done); in pci_snapshot_pci_dev()
2499 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.maxmsgnum, meta, ret, done); in pci_snapshot_pci_dev()
2501 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.enabled, meta, ret, done); in pci_snapshot_pci_dev()
2502 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_bar, meta, ret, done); in pci_snapshot_pci_dev()
2503 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_bar, meta, ret, done); in pci_snapshot_pci_dev()
2504 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_offset, meta, ret, done); in pci_snapshot_pci_dev()
2505 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_count, meta, ret, done); in pci_snapshot_pci_dev()
2506 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_offset, meta, ret, done); in pci_snapshot_pci_dev()
2507 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_size, meta, ret, done); in pci_snapshot_pci_dev()
2508 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.function_mask, meta, ret, done); in pci_snapshot_pci_dev()
2510 SNAPSHOT_BUF_OR_LEAVE(pi->pi_cfgdata, sizeof(pi->pi_cfgdata), in pci_snapshot_pci_dev()
2513 for (i = 0; i < (int)nitems(pi->pi_bar); i++) { in pci_snapshot_pci_dev()
2514 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].type, meta, ret, done); in pci_snapshot_pci_dev()
2515 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].size, meta, ret, done); in pci_snapshot_pci_dev()
2516 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].addr, meta, ret, done); in pci_snapshot_pci_dev()
2520 for (i = 0; i < pi->pi_msix.table_count; i++) { in pci_snapshot_pci_dev()
2521 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].addr, in pci_snapshot_pci_dev()
2523 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].msg_data, in pci_snapshot_pci_dev()
2525 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].vector_control, in pci_snapshot_pci_dev()
2598 pci_emul_dinit(struct pci_devinst *pi, nvlist_t *nvl __unused) in pci_emul_dinit() argument
2605 pi->pi_arg = sc; in pci_emul_dinit()
2607 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); in pci_emul_dinit()
2608 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); in pci_emul_dinit()
2609 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); in pci_emul_dinit()
2611 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); in pci_emul_dinit()
2614 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); in pci_emul_dinit()
2617 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); in pci_emul_dinit()
2620 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ); in pci_emul_dinit()
2627 pci_emul_diow(struct pci_devinst *pi, int baridx, uint64_t offset, int size, in pci_emul_diow() argument
2631 struct pci_emul_dsoftc *sc = pi->pi_arg; in pci_emul_diow()
2653 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) in pci_emul_diow()
2654 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi)); in pci_emul_diow()
2657 for (i = 0; i < pci_msi_maxmsgnum(pi); i++) in pci_emul_diow()
2658 pci_generate_msi(pi, i); in pci_emul_diow()
2694 pci_emul_dior(struct pci_devinst *pi, int baridx, uint64_t offset, int size) in pci_emul_dior() argument
2696 struct pci_emul_dsoftc *sc = pi->pi_arg; in pci_emul_dior()