Lines Matching full:pi

158 static void pci_lintr_route(struct pci_devinst *pi);
159 static void pci_lintr_update(struct pci_devinst *pi);
166 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes) in CFGWRITE() argument
170 pci_set_cfgdata8(pi, coff, val); in CFGWRITE()
172 pci_set_cfgdata16(pi, coff, val); in CFGWRITE()
174 pci_set_cfgdata32(pi, coff, val); in CFGWRITE()
178 CFGREAD(struct pci_devinst *pi, int coff, int bytes) in CFGREAD() argument
182 return (pci_get_cfgdata8(pi, coff)); in CFGREAD()
184 return (pci_get_cfgdata16(pi, coff)); in CFGREAD()
186 return (pci_get_cfgdata32(pi, coff)); in CFGREAD()
402 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) in pci_valid_pba_offset() argument
405 if (offset < pi->pi_msix.pba_offset) in pci_valid_pba_offset()
408 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { in pci_valid_pba_offset()
416 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, in pci_emul_msix_twrite() argument
431 if (tab_index >= pi->pi_msix.table_count) in pci_emul_msix_twrite()
440 dest = (char *)(pi->pi_msix.table + tab_index); in pci_emul_msix_twrite()
452 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) in pci_emul_msix_tread() argument
476 if (tab_index < pi->pi_msix.table_count) { in pci_emul_msix_tread()
478 dest = (char *)(pi->pi_msix.table + tab_index); in pci_emul_msix_tread()
487 } else if (pci_valid_pba_offset(pi, offset)) { in pci_emul_msix_tread()
496 pci_msix_table_bar(struct pci_devinst *pi) in pci_msix_table_bar() argument
499 if (pi->pi_msix.table != NULL) in pci_msix_table_bar()
500 return (pi->pi_msix.table_bar); in pci_msix_table_bar()
506 pci_msix_pba_bar(struct pci_devinst *pi) in pci_msix_pba_bar() argument
509 if (pi->pi_msix.table != NULL) in pci_msix_pba_bar()
510 return (pi->pi_msix.pba_bar); in pci_msix_pba_bar()
636 modify_bar_registration(struct pci_devinst *pi, int idx, int registration) in modify_bar_registration() argument
642 pe = pi->pi_d; in modify_bar_registration()
643 type = pi->pi_bar[idx].type; in modify_bar_registration()
651 iop.name = pi->pi_name; in modify_bar_registration()
652 iop.port = pi->pi_bar[idx].addr; in modify_bar_registration()
653 iop.size = pi->pi_bar[idx].size; in modify_bar_registration()
657 iop.arg = pi; in modify_bar_registration()
665 mr.name = pi->pi_name; in modify_bar_registration()
666 mr.base = pi->pi_bar[idx].addr; in modify_bar_registration()
667 mr.size = pi->pi_bar[idx].size; in modify_bar_registration()
671 mr.arg1 = pi; in modify_bar_registration()
685 mr.name = pi->pi_name; in modify_bar_registration()
686 mr.base = pi->pi_bar[idx].addr; in modify_bar_registration()
687 mr.size = pi->pi_bar[idx].size; in modify_bar_registration()
691 mr.arg1 = pi; in modify_bar_registration()
708 (*pe->pe_baraddr)(pi, idx, registration, pi->pi_bar[idx].addr); in modify_bar_registration()
712 unregister_bar(struct pci_devinst *pi, int idx) in unregister_bar() argument
715 modify_bar_registration(pi, idx, 0); in unregister_bar()
719 register_bar(struct pci_devinst *pi, int idx) in register_bar() argument
722 modify_bar_registration(pi, idx, 1); in register_bar()
727 romen(struct pci_devinst *pi) in romen() argument
729 return (pi->pi_bar[PCI_ROM_IDX].lobits & PCIM_BIOS_ENABLE) == in romen()
735 porten(struct pci_devinst *pi) in porten() argument
739 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); in porten()
746 memen(struct pci_devinst *pi) in memen() argument
750 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); in memen()
762 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) in update_bar_address() argument
766 if (pi->pi_bar[idx].type == PCIBAR_IO) in update_bar_address()
767 decode = porten(pi); in update_bar_address()
769 decode = memen(pi); in update_bar_address()
772 unregister_bar(pi, idx); in update_bar_address()
777 pi->pi_bar[idx].addr = addr; in update_bar_address()
780 pi->pi_bar[idx].addr &= ~0xffffffffUL; in update_bar_address()
781 pi->pi_bar[idx].addr |= addr; in update_bar_address()
784 pi->pi_bar[idx].addr &= 0xffffffff; in update_bar_address()
785 pi->pi_bar[idx].addr |= addr; in update_bar_address()
792 register_bar(pi, idx); in update_bar_address()
1045 pci_emul_add_boot_device(struct pci_devinst *pi, int bootindex) in pci_emul_add_boot_device() argument
1051 errx(4, "Invalid bootindex %d for %s", bootindex, pi->pi_name); in pci_emul_add_boot_device()
1059 new_device->pdi = pi; in pci_emul_add_boot_device()
1067 bootindex, pi->pi_name, device->pdi->pi_name); in pci_emul_add_boot_device()
1085 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) in pci_emul_add_capability() argument
1094 sts = pci_get_cfgdata16(pi, PCIR_STATUS); in pci_emul_add_capability()
1098 capoff = pi->pi_capend + 1; in pci_emul_add_capability()
1106 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); in pci_emul_add_capability()
1107 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); in pci_emul_add_capability()
1109 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff); in pci_emul_add_capability()
1113 pci_set_cfgdata8(pi, capoff + i, capdata[i]); in pci_emul_add_capability()
1116 pci_set_cfgdata8(pi, capoff + 1, 0); in pci_emul_add_capability()
1118 pi->pi_prevcap = capoff; in pci_emul_add_capability()
1119 pi->pi_capend = capoff + reallen - 1; in pci_emul_add_capability()
1191 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) in pci_emul_add_msicap() argument
1197 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); in pci_emul_add_msicap()
1227 pci_msix_table_init(struct pci_devinst *pi, int table_entries) in pci_msix_table_init() argument
1235 pi->pi_msix.table = calloc(1, table_size); in pci_msix_table_init()
1239 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; in pci_msix_table_init()
1243 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) in pci_emul_add_msixcap() argument
1256 pi->pi_msix.table_bar = barnum; in pci_emul_add_msixcap()
1257 pi->pi_msix.pba_bar = barnum; in pci_emul_add_msixcap()
1258 pi->pi_msix.table_offset = 0; in pci_emul_add_msixcap()
1259 pi->pi_msix.table_count = msgnum; in pci_emul_add_msixcap()
1260 pi->pi_msix.pba_offset = tab_size; in pci_emul_add_msixcap()
1261 pi->pi_msix.pba_size = PBA_SIZE(msgnum); in pci_emul_add_msixcap()
1263 pci_msix_table_init(pi, msgnum); in pci_emul_add_msixcap()
1268 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, in pci_emul_add_msixcap()
1269 tab_size + pi->pi_msix.pba_size); in pci_emul_add_msixcap()
1271 return (pci_emul_add_capability(pi, (u_char *)&msixcap, in pci_emul_add_msixcap()
1276 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, in msixcap_cfgwrite() argument
1286 msgctrl = pci_get_cfgdata16(pi, offset); in msixcap_cfgwrite()
1291 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; in msixcap_cfgwrite()
1292 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; in msixcap_cfgwrite()
1293 pci_lintr_update(pi); in msixcap_cfgwrite()
1296 CFGWRITE(pi, offset, val, bytes); in msixcap_cfgwrite()
1300 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, in msicap_cfgwrite() argument
1312 msgctrl = pci_get_cfgdata16(pi, offset); in msicap_cfgwrite()
1317 CFGWRITE(pi, offset, val, bytes); in msicap_cfgwrite()
1319 msgctrl = pci_get_cfgdata16(pi, capoff + 2); in msicap_cfgwrite()
1320 addrlo = pci_get_cfgdata32(pi, capoff + 4); in msicap_cfgwrite()
1322 msgdata = pci_get_cfgdata16(pi, capoff + 12); in msicap_cfgwrite()
1324 msgdata = pci_get_cfgdata16(pi, capoff + 8); in msicap_cfgwrite()
1327 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; in msicap_cfgwrite()
1328 if (pi->pi_msi.enabled) { in msicap_cfgwrite()
1329 pi->pi_msi.addr = addrlo; in msicap_cfgwrite()
1330 pi->pi_msi.msg_data = msgdata; in msicap_cfgwrite()
1331 pi->pi_msi.maxmsgnum = 1 << (mme >> 4); in msicap_cfgwrite()
1333 pi->pi_msi.maxmsgnum = 0; in msicap_cfgwrite()
1335 pci_lintr_update(pi); in msicap_cfgwrite()
1339 pciecap_cfgwrite(struct pci_devinst *pi, int capoff __unused, int offset, in pciecap_cfgwrite() argument
1344 CFGWRITE(pi, offset, val, bytes); in pciecap_cfgwrite()
1349 pci_emul_add_pciecap(struct pci_devinst *pi, int type) in pci_emul_add_pciecap() argument
1362 if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0)) in pci_emul_add_pciecap()
1372 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); in pci_emul_add_pciecap()
1382 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val, in pci_emul_capwrite() argument
1395 nextoff = pci_get_cfgdata8(pi, capoff + 1); in pci_emul_capwrite()
1404 capid = pci_get_cfgdata8(pi, capoff); in pci_emul_capwrite()
1424 msicap_cfgwrite(pi, capoff, offset, bytes, val); in pci_emul_capwrite()
1427 msixcap_cfgwrite(pi, capoff, offset, bytes, val); in pci_emul_capwrite()
1430 pciecap_cfgwrite(pi, capoff, offset, bytes, val); in pci_emul_capwrite()
1438 pci_emul_iscap(struct pci_devinst *pi, int offset) in pci_emul_iscap() argument
1442 sts = pci_get_cfgdata16(pi, PCIR_STATUS); in pci_emul_iscap()
1444 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend) in pci_emul_iscap()
1750 struct pci_devinst *pi; in pci_bus_write_dsdt() local
1886 pi = si->si_funcs[func].fi_devi; in pci_bus_write_dsdt()
1887 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL) in pci_bus_write_dsdt()
1888 pi->pi_d->pe_write_dsdt(pi); in pci_bus_write_dsdt()
1926 pci_msi_enabled(struct pci_devinst *pi) in pci_msi_enabled() argument
1928 return (pi->pi_msi.enabled); in pci_msi_enabled()
1932 pci_msi_maxmsgnum(struct pci_devinst *pi) in pci_msi_maxmsgnum() argument
1934 if (pi->pi_msi.enabled) in pci_msi_maxmsgnum()
1935 return (pi->pi_msi.maxmsgnum); in pci_msi_maxmsgnum()
1941 pci_msix_enabled(struct pci_devinst *pi) in pci_msix_enabled() argument
1944 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); in pci_msix_enabled()
1948 pci_generate_msix(struct pci_devinst *pi, int index) in pci_generate_msix() argument
1952 if (!pci_msix_enabled(pi)) in pci_generate_msix()
1955 if (pi->pi_msix.function_mask) in pci_generate_msix()
1958 if (index >= pi->pi_msix.table_count) in pci_generate_msix()
1961 mte = &pi->pi_msix.table[index]; in pci_generate_msix()
1964 vm_raise_msi(pi->pi_vmctx, mte->addr, mte->msg_data, in pci_generate_msix()
1965 pi->pi_bus, pi->pi_slot, pi->pi_func); in pci_generate_msix()
1970 pci_generate_msi(struct pci_devinst *pi, int index) in pci_generate_msi() argument
1973 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) { in pci_generate_msi()
1974 vm_raise_msi(pi->pi_vmctx, pi->pi_msi.addr, in pci_generate_msi()
1975 pi->pi_msi.msg_data + index, in pci_generate_msi()
1976 pi->pi_bus, pi->pi_slot, pi->pi_func); in pci_generate_msi()
1981 pci_lintr_permitted(struct pci_devinst *pi) in pci_lintr_permitted() argument
1985 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); in pci_lintr_permitted()
1986 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled || in pci_lintr_permitted()
1991 pci_lintr_request(struct pci_devinst *pi) in pci_lintr_request() argument
1997 bi = pci_businfo[pi->pi_bus]; in pci_lintr_request()
2004 si = &bi->slotinfo[pi->pi_slot]; in pci_lintr_request()
2015 pi->pi_lintr.pin = bestpin + 1; in pci_lintr_request()
2016 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1); in pci_lintr_request()
2020 pci_lintr_route(struct pci_devinst *pi) in pci_lintr_route() argument
2026 if (pi->pi_lintr.pin == 0) in pci_lintr_route()
2029 bi = pci_businfo[pi->pi_bus]; in pci_lintr_route()
2031 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1]; in pci_lintr_route()
2033 pci_irq_route(pi, irq); in pci_lintr_route()
2034 pi->pi_lintr.irq = *irq; in pci_lintr_route()
2035 pci_set_cfgdata8(pi, PCIR_INTLINE, pci_irq_intline(irq)); in pci_lintr_route()
2039 pci_lintr_assert(struct pci_devinst *pi) in pci_lintr_assert() argument
2042 assert(pi->pi_lintr.pin > 0); in pci_lintr_assert()
2044 pthread_mutex_lock(&pi->pi_lintr.lock); in pci_lintr_assert()
2045 if (pi->pi_lintr.state == IDLE) { in pci_lintr_assert()
2046 if (pci_lintr_permitted(pi)) { in pci_lintr_assert()
2047 pi->pi_lintr.state = ASSERTED; in pci_lintr_assert()
2048 pci_irq_assert(pi); in pci_lintr_assert()
2050 pi->pi_lintr.state = PENDING; in pci_lintr_assert()
2052 pthread_mutex_unlock(&pi->pi_lintr.lock); in pci_lintr_assert()
2056 pci_lintr_deassert(struct pci_devinst *pi) in pci_lintr_deassert() argument
2059 assert(pi->pi_lintr.pin > 0); in pci_lintr_deassert()
2061 pthread_mutex_lock(&pi->pi_lintr.lock); in pci_lintr_deassert()
2062 if (pi->pi_lintr.state == ASSERTED) { in pci_lintr_deassert()
2063 pi->pi_lintr.state = IDLE; in pci_lintr_deassert()
2064 pci_irq_deassert(pi); in pci_lintr_deassert()
2065 } else if (pi->pi_lintr.state == PENDING) in pci_lintr_deassert()
2066 pi->pi_lintr.state = IDLE; in pci_lintr_deassert()
2067 pthread_mutex_unlock(&pi->pi_lintr.lock); in pci_lintr_deassert()
2071 pci_lintr_update(struct pci_devinst *pi) in pci_lintr_update() argument
2074 pthread_mutex_lock(&pi->pi_lintr.lock); in pci_lintr_update()
2075 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) { in pci_lintr_update()
2076 pci_irq_deassert(pi); in pci_lintr_update()
2077 pi->pi_lintr.state = PENDING; in pci_lintr_update()
2078 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) { in pci_lintr_update()
2079 pi->pi_lintr.state = ASSERTED; in pci_lintr_update()
2080 pci_irq_assert(pi); in pci_lintr_update()
2082 pthread_mutex_unlock(&pi->pi_lintr.lock); in pci_lintr_update()
2182 pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old) in pci_emul_cmd_changed() argument
2187 new = pci_get_cfgdata16(pi, PCIR_COMMAND); in pci_emul_cmd_changed()
2195 switch (pi->pi_bar[i].type) { in pci_emul_cmd_changed()
2203 register_bar(pi, i); in pci_emul_cmd_changed()
2205 unregister_bar(pi, i); in pci_emul_cmd_changed()
2210 if (!romen(pi)) in pci_emul_cmd_changed()
2218 register_bar(pi, i); in pci_emul_cmd_changed()
2220 unregister_bar(pi, i); in pci_emul_cmd_changed()
2232 pci_lintr_update(pi); in pci_emul_cmd_changed()
2236 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes) in pci_emul_cmdsts_write() argument
2241 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ in pci_emul_cmdsts_write()
2253 old = CFGREAD(pi, coff, bytes); in pci_emul_cmdsts_write()
2256 CFGWRITE(pi, coff, new, bytes); /* update config */ in pci_emul_cmdsts_write()
2258 pci_emul_cmd_changed(pi, cmd); in pci_emul_cmdsts_write()
2267 struct pci_devinst *pi; in pci_cfgrw() local
2274 pi = si->si_funcs[func].fi_devi; in pci_cfgrw()
2276 pi = NULL; in pci_cfgrw()
2282 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) || in pci_cfgrw()
2308 pe = pi->pi_d; in pci_cfgrw()
2316 needcfg = pe->pe_cfgread(pi, coff, bytes, valp); in pci_cfgrw()
2322 *valp = CFGREAD(pi, coff, bytes); in pci_cfgrw()
2328 (*pe->pe_cfgwrite)(pi, coff, bytes, *valp) == 0) in pci_cfgrw()
2351 mask = ~(pi->pi_bar[idx].size - 1); in pci_cfgrw()
2352 switch (pi->pi_bar[idx].type) { in pci_cfgrw()
2354 pi->pi_bar[idx].addr = bar = 0; in pci_cfgrw()
2361 bar = addr | pi->pi_bar[idx].lobits; in pci_cfgrw()
2365 if (addr != pi->pi_bar[idx].addr) { in pci_cfgrw()
2366 update_bar_address(pi, addr, idx, in pci_cfgrw()
2372 bar |= pi->pi_bar[idx].lobits; in pci_cfgrw()
2373 if (addr != pi->pi_bar[idx].addr) { in pci_cfgrw()
2374 update_bar_address(pi, addr, idx, in pci_cfgrw()
2380 bar |= pi->pi_bar[idx].lobits; in pci_cfgrw()
2381 if (addr != (uint32_t)pi->pi_bar[idx].addr) { in pci_cfgrw()
2382 update_bar_address(pi, addr, idx, in pci_cfgrw()
2387 mask = ~(pi->pi_bar[idx - 1].size - 1); in pci_cfgrw()
2390 if (bar != pi->pi_bar[idx - 1].addr >> 32) { in pci_cfgrw()
2391 update_bar_address(pi, addr, idx - 1, in pci_cfgrw()
2397 if (memen(pi) && romen(pi)) { in pci_cfgrw()
2398 unregister_bar(pi, idx); in pci_cfgrw()
2400 pi->pi_bar[idx].addr = addr; in pci_cfgrw()
2401 pi->pi_bar[idx].lobits = *valp & in pci_cfgrw()
2404 if (memen(pi) && romen(pi)) { in pci_cfgrw()
2405 register_bar(pi, idx); in pci_cfgrw()
2407 bar |= pi->pi_bar[idx].lobits; in pci_cfgrw()
2412 pci_set_cfgdata32(pi, coff, bar); in pci_cfgrw()
2414 } else if (pci_emul_iscap(pi, coff)) { in pci_cfgrw()
2415 pci_emul_capwrite(pi, coff, bytes, *valp, 0, 0); in pci_cfgrw()
2417 pci_emul_cmdsts_write(pi, coff, *valp, bytes); in pci_cfgrw()
2419 CFGWRITE(pi, coff, *valp, bytes); in pci_cfgrw()
2489 struct pci_devinst *pi; in pci_snapshot_pci_dev() local
2493 pi = meta->dev_data; in pci_snapshot_pci_dev()
2495 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.enabled, meta, ret, done); in pci_snapshot_pci_dev()
2496 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.addr, meta, ret, done); in pci_snapshot_pci_dev()
2497 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.msg_data, meta, ret, done); in pci_snapshot_pci_dev()
2498 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.maxmsgnum, meta, ret, done); in pci_snapshot_pci_dev()
2500 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.enabled, meta, ret, done); in pci_snapshot_pci_dev()
2501 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_bar, meta, ret, done); in pci_snapshot_pci_dev()
2502 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_bar, meta, ret, done); in pci_snapshot_pci_dev()
2503 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_offset, meta, ret, done); in pci_snapshot_pci_dev()
2504 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_count, meta, ret, done); in pci_snapshot_pci_dev()
2505 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_offset, meta, ret, done); in pci_snapshot_pci_dev()
2506 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_size, meta, ret, done); in pci_snapshot_pci_dev()
2507 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.function_mask, meta, ret, done); in pci_snapshot_pci_dev()
2509 SNAPSHOT_BUF_OR_LEAVE(pi->pi_cfgdata, sizeof(pi->pi_cfgdata), in pci_snapshot_pci_dev()
2512 for (i = 0; i < (int)nitems(pi->pi_bar); i++) { in pci_snapshot_pci_dev()
2513 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].type, meta, ret, done); in pci_snapshot_pci_dev()
2514 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].size, meta, ret, done); in pci_snapshot_pci_dev()
2515 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].addr, meta, ret, done); in pci_snapshot_pci_dev()
2519 for (i = 0; i < pi->pi_msix.table_count; i++) { in pci_snapshot_pci_dev()
2520 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].addr, in pci_snapshot_pci_dev()
2522 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].msg_data, in pci_snapshot_pci_dev()
2524 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].vector_control, in pci_snapshot_pci_dev()
2597 pci_emul_dinit(struct pci_devinst *pi, nvlist_t *nvl __unused) in pci_emul_dinit() argument
2604 pi->pi_arg = sc; in pci_emul_dinit()
2606 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); in pci_emul_dinit()
2607 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); in pci_emul_dinit()
2608 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); in pci_emul_dinit()
2610 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); in pci_emul_dinit()
2613 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); in pci_emul_dinit()
2616 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); in pci_emul_dinit()
2619 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ); in pci_emul_dinit()
2626 pci_emul_diow(struct pci_devinst *pi, int baridx, uint64_t offset, int size, in pci_emul_diow() argument
2630 struct pci_emul_dsoftc *sc = pi->pi_arg; in pci_emul_diow()
2652 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) in pci_emul_diow()
2653 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi)); in pci_emul_diow()
2656 for (i = 0; i < pci_msi_maxmsgnum(pi); i++) in pci_emul_diow()
2657 pci_generate_msi(pi, i); in pci_emul_diow()
2693 pci_emul_dior(struct pci_devinst *pi, int baridx, uint64_t offset, int size) in pci_emul_dior() argument
2695 struct pci_emul_dsoftc *sc = pi->pi_arg; in pci_emul_dior()