Lines Matching +full:0 +full:x3c8
32 #define VGA_IOPORT_START 0x3c0
33 #define VGA_IOPORT_END 0x3df
36 #define GEN_INPUT_STS0_PORT 0x3c2
37 #define GEN_FEATURE_CTRL_PORT 0x3ca
38 #define GEN_MISC_OUTPUT_PORT 0x3cc
39 #define GEN_INPUT_STS1_MONO_PORT 0x3ba
40 #define GEN_INPUT_STS1_COLOR_PORT 0x3da
41 #define GEN_IS1_VR 0x08 /* Vertical retrace */
42 #define GEN_IS1_DE 0x01 /* Display enable not */
45 #define ATC_IDX_PORT 0x3c0
46 #define ATC_DATA_PORT 0x3c1
48 #define ATC_IDX_MASK 0x1f
49 #define ATC_PALETTE0 0
52 #define ATC_MC_IPS 0x80 /* Internal palette size */
53 #define ATC_MC_GA 0x01 /* Graphics/alphanumeric */
58 #define ATC_CS_C67 0x0c /* Color select bits 6+7 */
59 #define ATC_CS_C45 0x03 /* Color select bits 4+5 */
62 #define SEQ_IDX_PORT 0x3c4
63 #define SEQ_DATA_PORT 0x3c5
65 #define SEQ_RESET 0
66 #define SEQ_RESET_ASYNC 0x1
67 #define SEQ_RESET_SYNC 0x2
69 #define SEQ_CM_SO 0x20 /* Screen off */
70 #define SEQ_CM_89 0x01 /* 8/9 dot clock */
73 #define SEQ_CMS_SAH 0x20 /* Char map A bit 2 */
75 #define SEQ_CMS_SA 0x0c /* Char map A bits 0+1 */
77 #define SEQ_CMS_SBH 0x10 /* Char map B bit 2 */
79 #define SEQ_CMS_SB 0x03 /* Char map B bits 0+1 */
80 #define SEQ_CMS_SB_SHIFT 0
82 #define SEQ_MM_C4 0x08 /* Chain 4 */
83 #define SEQ_MM_OE 0x04 /* Odd/even */
84 #define SEQ_MM_EM 0x02 /* Extended memory */
87 #define GC_IDX_PORT 0x3ce
88 #define GC_DATA_PORT 0x3cf
90 #define GC_SET_RESET 0
96 #define GC_MODE_OE 0x10 /* Odd/even */
97 #define GC_MODE_C4 0x04 /* Chain 4 */
100 #define GC_MISC_GM 0x01 /* Graphics/alphanumeric */
101 #define GC_MISC_MM 0x0c /* memory map */
107 #define CRTC_IDX_MONO_PORT 0x3b4
108 #define CRTC_DATA_MONO_PORT 0x3b5
109 #define CRTC_IDX_COLOR_PORT 0x3d4
110 #define CRTC_DATA_COLOR_PORT 0x3d5
112 #define CRTC_HORIZ_TOTAL 0
120 #define CRTC_OF_VRS9 0x80 /* VRS bit 9 */
122 #define CRTC_OF_VDE9 0x40 /* VDE bit 9 */
124 #define CRTC_OF_VRS8 0x04 /* VRS bit 8 */
126 #define CRTC_OF_VDE8 0x02 /* VDE bit 8 */
130 #define CRTC_MSL_MSL 0x1f
132 #define CRTC_CS_CO 0x20 /* Cursor off */
133 #define CRTC_CS_CS 0x1f /* Cursor start */
135 #define CRTC_CE_CE 0x1f /* Cursor end */
142 #define CRTC_VRE_MASK 0xf
149 #define CRTC_MC_TE 0x80 /* Timing enable */
153 #define DAC_MASK 0x3c6
154 #define DAC_IDX_RD_PORT 0x3c7
155 #define DAC_IDX_WR_PORT 0x3c8
156 #define DAC_DATA_PORT 0x3c9