54 #define	IO_ICU1		0x20
55 #define	IO_ICU2		0xA0
60 #define	ELCR_PORT	0x4d0
63 #define	IO_TIMER1_PORT	0x40
65 #define	NMISC_PORT	0x61
102 		if (strcasecmp(lpcdev, "bootrom") == 0) {  in lpc_device_parse()
111 				error = 0;  in lpc_device_parse()
124 			error = 0;  in lpc_device_parse()
127 		if (strcasecmp(lpcdev, "tpm") == 0) {  in lpc_device_parse()
145 			error = 0;  in lpc_device_parse()
148 		for (unit = 0; unit < LPC_UART_NUM; unit++) {  in lpc_device_parse()
149 			if (strcasecmp(lpcdev, lpc_uart_names[unit]) == 0) {  in lpc_device_parse()
154 				error = 0;  in lpc_device_parse()
158 		if (strcasecmp(lpcdev, pctestdev_getname()) == 0) {  in lpc_device_parse()
162 			error = 0;  in lpc_device_parse()
179 	for (i = 0; i < LPC_UART_NUM; i++)  in lpc_print_supported_devices()
196 	assert(sc->irq >= 0);  in lpc_uart_intr_assert()
241 	return (0);  in lpc_uart_io_handler()
254 	for (unit = 0; unit < LPC_UART_NUM; unit++) {  in lpc_init()
258 		if (uart_legacy_alloc(unit, &sc->iobase, &sc->irq) != 0) {  in lpc_init()
272 		    uart_ns16550_tty_open(sc->uart_softc, backend) != 0) {  in lpc_init()
287 		assert(error == 0);  in lpc_init()
300 	return (0);  in lpc_init()
311 	dsdt_line("  Name (_ADR, 0x%04X%04X)", pi->pi_slot, pi->pi_func);  in pci_lpc_write_dsdt()
312 	dsdt_line("  OperationRegion (LPCR, PCI_Config, 0x00, 0x100)");  in pci_lpc_write_dsdt()
315 	dsdt_line("    Offset (0x60),");  in pci_lpc_write_dsdt()
320 	dsdt_line("    Offset (0x68),");  in pci_lpc_write_dsdt()
356 	dsdt_fixed_irq(0);  in pci_lpc_write_dsdt()
402 	for (unit = 0; unit < LPC_UART_NUM; unit++) {  in pci_lpc_uart_dsdt()
429 		pirq_pin = 0;  in pci_lpc_cfgwrite()
430 		if (coff >= 0x60 && coff <= 0x63)  in pci_lpc_cfgwrite()
431 			pirq_pin = coff - 0x60 + 1;  in pci_lpc_cfgwrite()
432 		if (coff >= 0x68 && coff <= 0x6b)  in pci_lpc_cfgwrite()
433 			pirq_pin = coff - 0x68 + 5;  in pci_lpc_cfgwrite()
434 		if (pirq_pin != 0) {  in pci_lpc_cfgwrite()
437 			return (0);  in pci_lpc_cfgwrite()
453 	return (0);  in pci_lpc_read()
456 #define	LPC_DEV		0x7000
457 #define	LPC_VENDOR	0x8086
458 #define LPC_REVID	0x00
459 #define LPC_SUBVEND_0	0x0000
460 #define LPC_SUBDEV_0	0x0000
467 	memset(sel, 0, sizeof(*sel));  in pci_lpc_get_sel()
469 	for (uint8_t slot = 0; slot <= PCI_SLOTMAX; ++slot) {  in pci_lpc_get_sel()
470 		uint8_t max_func = 0;  in pci_lpc_get_sel()
473 		sel->pc_func = 0;  in pci_lpc_get_sel()
478 		for (uint8_t func = 0; func <= max_func; ++func) {  in pci_lpc_get_sel()
485 				return (0);  in pci_lpc_get_sel()
498 	struct pcisel sel = { 0 };  in pci_lpc_init()
512 	 * Enforce that the LPC can only be configured on bus 0. This  in pci_lpc_init()
514 	 * all legacy i/o ports behind bus 0.  in pci_lpc_init()
516 	if (pi->pi_bus != 0) {  in pci_lpc_init()
517 		EPRINTLN("LPC bridge can be present only on bus 0.");  in pci_lpc_init()
521 	if (lpc_init(pi->pi_vmctx) != 0)  in pci_lpc_init()
524 	if (pci_lpc_get_sel(&sel) == 0)  in pci_lpc_init()
546 	return (0);  in pci_lpc_init()
568  	for (pin = 0; pin < 4; pin++)  in lpc_pirq_routed()
569 		pci_set_cfgdata8(lpc_bridge, 0x60 + pin, pirq_read(pin + 1));  in lpc_pirq_routed()
570 	for (pin = 0; pin < 4; pin++)  in lpc_pirq_routed()
571 		pci_set_cfgdata8(lpc_bridge, 0x68 + pin, pirq_read(pin + 5));  in lpc_pirq_routed()
581 	for (unit = 0; unit < LPC_UART_NUM; unit++) {  in pci_lpc_snapshot()
585 		if (ret != 0)  in pci_lpc_snapshot()