1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
4  * Copyright (c) 2013-2015 The FreeBSD Foundation
39 #define	DMAR_ROOT_R1_CTP_MASK	0xfffffffffffff000 /* Mask for Context-Entry
54 #define	DMAR_CTX1_T_PASS	8		/* Pass-Through */
55 #define	DMAR_CTX1_ASR_MASK	0xfffffffffffff000 /* Mask for the Address
57 #define	DMAR_CTX2_AW_2LVL	0		/* 2-level page tables */
58 #define	DMAR_CTX2_AW_3LVL	1		/* 3-level page tables */
59 #define	DMAR_CTX2_AW_4LVL	2		/* 4-level page tables */
60 #define	DMAR_CTX2_AW_5LVL	3		/* 5-level page tables */
61 #define	DMAR_CTX2_AW_6LVL	4		/* 6-level page tables */
63 #define	DMAR_CTX2_DID(x)	((x) << 8)	/* Domain Identifier */  argument
70 #define	DMAR_PTE_ADDR_MASK	0xffffffffff000	/* Address Mask */
78 #define	DMAR_IRTE2_SVT_NONE	(0ULL << (82 - 64))
79 #define	DMAR_IRTE2_SVT_RID	(1ULL << (82 - 64))
80 #define	DMAR_IRTE2_SVT_BUS	(2ULL << (82 - 64))
81 /* Source-id Qualifier */
82 #define	DMAR_IRTE2_SQ_RID	(0ULL << (80 - 64))
83 #define	DMAR_IRTE2_SQ_RID_N2	(1ULL << (80 - 64))
84 #define	DMAR_IRTE2_SQ_RID_N21	(2ULL << (80 - 64))
85 #define	DMAR_IRTE2_SQ_RID_N210	(3ULL << (80 - 64))
87 #define	DMAR_IRTE2_SID_RID(x)	((uint64_t)(x))  argument
90 #define	DMAR_IRTE1_DST_xAPIC(x)	(((uint64_t)(x)) << 40)  argument
91 #define	DMAR_IRTE1_DST_x2APIC(x) (((uint64_t)(x)) << 32)  argument
93 #define	DMAR_IRTE1_V(x)		(((uint64_t)x) << 16)  argument
116 #define	DMAR_MAJOR_VER(x)	(((x) >> 4) & 0xf)  argument
117 #define	DMAR_MINOR_VER(x)	((x) & 0xf)  argument
125 #define	DMAR_CAP_MAMV(x) ((u_int)(((x) >> 48) & 0x3f))  argument
126 					/* Maximum Address Mask */
127 #define	DMAR_CAP_NFR(x)	((u_int)(((x) >> 40) & 0xff) + 1)  argument
128 					/* Num of Fault-recording regs */
130 #define	DMAR_CAP_SPS(x)	((u_int)(((x) >> 34) & 0xf)) /* Super-Page Support */  argument
135 #define	DMAR_CAP_FRO(x)	((u_int)(((x) >> 24) & 0x1ff))  argument
136 					/* Fault-recording reg offset */
138 #define	DMAR_CAP_ZLR	(1 << 22)	/* Zero-length reads */
139 #define	DMAR_CAP_MGAW(x) ((u_int)(((x) >> 16) & 0x3f))  argument
141 #define DMAR_CAP_SAGAW(x) ((u_int)(((x) >> 8) & 0x1f))  argument
149 #define	DMAR_CAP_PHMR	(1 << 6)	/* Protected High-mem Region */
150 #define	DMAR_CAP_PLMR	(1 << 5)	/* Protected Low-mem Region */
151 #define	DMAR_CAP_RWBF	(1 << 4)	/* Required Write-Buffer Flushing */
153 #define	DMAR_CAP_ND(x)	((u_int)((x) & 0x3))	/* Number of domains */  argument
157 #define	DMAR_ECAP_PSS(x) (((x) >> 35) & 0xf) /* PASID Size Supported */  argument
168 #define	DMAR_ECAP_MHMV(x) ((u_int)(((x) >> 20) & 0xf))  argument
169 					/* Maximum Handle Mask Value */
170 #define	DMAR_ECAP_IRO(x)  ((u_int)(((x) >> 8) & 0x3ff))  argument
206 /* Root-Entry Table Address register */
213 #define	DMAR_CCMD_ICC	(1ULL << 63)	/* Invalidate Context-Cache */
220 #define	DMAR_CCMD_CAIG(x)	(((x) >> 59) & 0x3) /* Context Actual  argument
225 #define	DMAR_CCMD_FM		(0x3UUL << 32)	/* Function Mask */
226 #define	DMAR_CCMD_SID(x)	(((x) & 0xffff) << 16) /* Source-ID */  argument
227 #define	DMAR_CCMD_DID(x)	((x) & 0xffff)	/* Domain-ID */  argument
232 #define	DMAR_IVA_AM(x)		((x) & 0x1f)	/* Address Mask */  argument
233 #define	DMAR_IVA_ADDR(x)	((x) & ~0xfffULL) /* Address */  argument
242 #define	DMAR_IOTLB_IIRG_DOM	(0x2ULL << 60)	/* Domain-selective */
243 #define	DMAR_IOTLB_IIRG_PAGE	(0x3ULL << 60)	/* Page-selective */
248 #define	DMAR_IOTLB_IAIG_DOM	(0x2ULL << 57)	/* Domain-selective */
249 #define	DMAR_IOTLB_IAIG_PAGE	(0x3ULL << 57)	/* Page-selective */
252 #define	DMAR_IOTLB_DID(x)	(((uint64_t)(x) & 0xffff) << 32) /* Domain Id */  argument
256 #define	DMAR_FSTS_FRI(x)	(((x) >> 8) & 0xff) /* Fault Record Index */  argument
257 #define	DMAR_FSTS_ITE		(1 << 6)	/* Invalidation Time-out */
267 #define	DMAR_FECTL_IM		(1U << 31)	/* Interrupt Mask */
285 #define	DMAR_FRCD2_T(x)		((int)((x >> 62) & 1))	/* Type */  argument
288 #define	DMAR_FRCD2_AT(x)	((int)((x >> 60) & 0x3)) /* Address Type */  argument
289 #define	DMAR_FRCD2_FR(x)	((int)((x >> 32) & 0xff)) /* Fault Reason */  argument
290 #define	DMAR_FRCD2_SID(x)	((int)(x & 0xffff))	/* Source Identifier */  argument
291 #define	DMAR_FRCS1_FI_MASK	0xffffffffff000	/* Fault Info, Address Mask */
298 /* Protected Low-Memory Base register */
301 /* Protected Low-Memory Limit register */
304 /* Protected High-Memory Base register */
307 /* Protected High-Memory Limit register */
316 /* Context-cache Invalidate Descriptor */
321 #define	DMAR_IQ_DESCR_CTX_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */  argument
322 #define	DMAR_IQ_DESCR_CTX_SRC(x) (((uint64_t)(x)) << 32) /* Source Id */  argument
323 #define	DMAR_IQ_DESCR_CTX_FM(x)  (((uint64_t)(x)) << 48) /* Function Mask */  argument
332 #define	DMAR_IQ_DESCR_IOTLB_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */  argument
334 /* Device-TLB Invalidate Descriptor */
339 #define	DMAR_IQ_DESCR_IEC_IDX	(1 << 4) /* Index-Selective Invalidation */
340 #define	DMAR_IQ_DESCR_IEC_IIDX(x) (((uint64_t)x) << 32) /* Interrupt Index */  argument
341 #define	DMAR_IQ_DESCR_IEC_IM(x)	((x) << 27)	/* Index Mask */  argument
348 #define	DMAR_IQ_DESCR_WAIT_SD(x) (((uint64_t)(x)) << 32) /* Status Data */  argument
353 /* PASID-Cache Invalidate Descriptor */
356 /* Extended Device-TLB Invalidate Descriptor */
361 #define	DMAR_IQH_MASK		0x7fff0		/* Next cmd index mask */
370 						      Base Address mask */
382 #define	DMAR_IECTL_IM		(1U << 31)	/* Interrupt Mask */
398 #define	DMAR_IRTA_S_MASK	0xf		/* Size Mask */