Lines Matching full:invalidation
129 #define DMAR_CAP_PSI (1ULL << 39) /* Page Selective Invalidation */
177 #define DMAR_ECAP_QI (1 << 1) /* Queued Invalidation */
187 #define DMAR_GCMD_QIE (1 << 26) /* Queued Invalidation Enable */
199 #define DMAR_GSTS_QIES (1 << 26) /* Queued Invalidation Enable Status */
215 #define DMAR_CCMD_CIRG_MASK (0x3ULL << 61) /* Context Invalidation
221 Invalidation Granularity */
231 #define DMAR_IVA_IH (1 << 6) /* Invalidation Hint */
239 #define DMAR_IOTLB_IIRG_MASK (0x3ULL << 60) /* Invalidation Request
244 #define DMAR_IOTLB_IAIG_MASK (0x3ULL << 57) /* Actual Invalidation
257 #define DMAR_FSTS_ITE (1 << 6) /* Invalidation Time-out */
258 #define DMAR_FSTS_ICE (1 << 5) /* Invalidation Completion */
259 #define DMAR_FSTS_IQE (1 << 4) /* Invalidation Queue */
310 /* Queued Invalidation Descriptors */
339 #define DMAR_IQ_DESCR_IEC_IDX (1 << 4) /* Index-Selective Invalidation */
343 /* Invalidation Wait Descriptor */
359 /* Invalidation Queue Head register */
363 /* Invalidation Queue Tail register */
367 /* Invalidation Queue Address register */
369 #define DMAR_IQA_IQA_MASK 0xfffffffffffff000 /* Invalidation Queue
375 /* Invalidation Completion Status register */
377 #define DMAR_ICS_IWC 1 /* Invalidation Wait
380 /* Invalidation Event Control register */
385 /* Invalidation Event Data register */
388 /* Invalidation Event Address register */
391 /* Invalidation Event Upper Address register */