Lines Matching refs:unit
266 dmar_release_resources(device_t dev, struct dmar_unit *unit) in dmar_release_resources() argument
270 iommu_fini_busdma(&unit->iommu); in dmar_release_resources()
271 dmar_fini_irt(unit); in dmar_release_resources()
272 dmar_fini_qi(unit); in dmar_release_resources()
273 dmar_fini_fault_log(unit); in dmar_release_resources()
275 iommu_release_intr(DMAR2IOMMU(unit), i); in dmar_release_resources()
276 if (unit->regs != NULL) { in dmar_release_resources()
277 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid, in dmar_release_resources()
278 unit->regs); in dmar_release_resources()
279 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid, in dmar_release_resources()
280 unit->regs); in dmar_release_resources()
281 unit->regs = NULL; in dmar_release_resources()
283 if (unit->domids != NULL) { in dmar_release_resources()
284 delete_unrhdr(unit->domids); in dmar_release_resources()
285 unit->domids = NULL; in dmar_release_resources()
287 if (unit->ctx_obj != NULL) { in dmar_release_resources()
288 vm_object_deallocate(unit->ctx_obj); in dmar_release_resources()
289 unit->ctx_obj = NULL; in dmar_release_resources()
291 sysctl_ctx_free(&unit->iommu.sysctl_ctx); in dmar_release_resources()
298 struct dmar_unit *unit; in dmar_remap_intr() local
304 unit = device_get_softc(dev); in dmar_remap_intr()
306 dmd = &unit->x86c.intrs[i]; in dmar_remap_intr()
313 DMAR_LOCK(unit); in dmar_remap_intr()
316 (dmd->disable_intr)(DMAR2IOMMU(unit)); in dmar_remap_intr()
317 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data); in dmar_remap_intr()
318 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr); in dmar_remap_intr()
319 dmar_write4(unit, dmd->msi_uaddr_reg, in dmar_remap_intr()
321 (dmd->enable_intr)(DMAR2IOMMU(unit)); in dmar_remap_intr()
322 DMAR_UNLOCK(unit); in dmar_remap_intr()
331 dmar_print_caps(device_t dev, struct dmar_unit *unit, in dmar_print_caps() argument
337 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver), in dmar_print_caps()
338 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment, in dmar_print_caps()
340 caphi = unit->hw_cap >> 32; in dmar_print_caps()
341 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap, in dmar_print_caps()
345 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap), in dmar_print_caps()
346 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap), in dmar_print_caps()
347 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap)); in dmar_print_caps()
348 if ((unit->hw_cap & DMAR_CAP_PSI) != 0) in dmar_print_caps()
349 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap)); in dmar_print_caps()
351 ecaphi = unit->hw_ecap >> 32; in dmar_print_caps()
352 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap, in dmar_print_caps()
356 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap), in dmar_print_caps()
357 DMAR_ECAP_IRO(unit->hw_ecap)); in dmar_print_caps()
363 struct dmar_unit *unit; in dmar_attach() local
370 unit = device_get_softc(dev); in dmar_attach()
371 unit->iommu.unit = device_get_unit(dev); in dmar_attach()
372 unit->iommu.dev = dev; in dmar_attach()
373 sysctl_ctx_init(&unit->iommu.sysctl_ctx); in dmar_attach()
374 dmaru = dmar_find_by_index(unit->iommu.unit); in dmar_attach()
377 unit->segment = dmaru->Segment; in dmar_attach()
378 unit->base = dmaru->Address; in dmar_attach()
379 unit->reg_rid = DMAR_REG_RID; in dmar_attach()
380 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, in dmar_attach()
381 &unit->reg_rid, RF_ACTIVE); in dmar_attach()
382 if (unit->regs == NULL) { in dmar_attach()
384 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
387 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG); in dmar_attach()
388 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG); in dmar_attach()
389 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG); in dmar_attach()
391 dmar_print_caps(dev, unit, dmaru); in dmar_attach()
392 dmar_quirks_post_ident(unit); in dmar_attach()
393 unit->memdomain = acpi_get_domain(dev); in dmar_attach()
399 unit->x86c.intrs[i].irq = -1; in dmar_attach()
401 dmd = &unit->x86c.intrs[DMAR_INTR_FAULT]; in dmar_attach()
410 error = iommu_alloc_irq(DMAR2IOMMU(unit), DMAR_INTR_FAULT); in dmar_attach()
412 dmar_release_resources(dev, unit); in dmar_attach()
413 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
416 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data); in dmar_attach()
417 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr); in dmar_attach()
418 dmar_write4(unit, dmd->msi_uaddr_reg, dmd->msi_addr >> 32); in dmar_attach()
420 if (DMAR_HAS_QI(unit)) { in dmar_attach()
421 dmd = &unit->x86c.intrs[DMAR_INTR_QI]; in dmar_attach()
430 error = iommu_alloc_irq(DMAR2IOMMU(unit), DMAR_INTR_QI); in dmar_attach()
432 dmar_release_resources(dev, unit); in dmar_attach()
433 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
437 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data); in dmar_attach()
438 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr); in dmar_attach()
439 dmar_write4(unit, dmd->msi_uaddr_reg, dmd->msi_addr >> 32); in dmar_attach()
442 mtx_init(&unit->iommu.lock, "dmarhw", NULL, MTX_DEF); in dmar_attach()
443 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)), in dmar_attach()
444 &unit->iommu.lock); in dmar_attach()
445 LIST_INIT(&unit->domains); in dmar_attach()
454 if ((unit->hw_cap & DMAR_CAP_CM) != 0) in dmar_attach()
455 alloc_unr_specific(unit->domids, 0); in dmar_attach()
457 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 + in dmar_attach()
459 if (unit->memdomain != -1) { in dmar_attach()
460 unit->ctx_obj->domain.dr_policy = DOMAINSET_PREF( in dmar_attach()
461 unit->memdomain); in dmar_attach()
469 iommu_pgalloc(unit->ctx_obj, 0, IOMMU_PGF_WAITOK | IOMMU_PGF_ZERO); in dmar_attach()
470 DMAR_LOCK(unit); in dmar_attach()
471 error = dmar_load_root_entry_ptr(unit); in dmar_attach()
473 DMAR_UNLOCK(unit); in dmar_attach()
474 dmar_release_resources(dev, unit); in dmar_attach()
475 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
478 error = dmar_inv_ctx_glob(unit); in dmar_attach()
480 DMAR_UNLOCK(unit); in dmar_attach()
481 dmar_release_resources(dev, unit); in dmar_attach()
482 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
485 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) { in dmar_attach()
486 error = dmar_inv_iotlb_glob(unit); in dmar_attach()
488 DMAR_UNLOCK(unit); in dmar_attach()
489 dmar_release_resources(dev, unit); in dmar_attach()
490 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
495 DMAR_UNLOCK(unit); in dmar_attach()
496 error = dmar_init_fault_log(unit); in dmar_attach()
498 dmar_release_resources(dev, unit); in dmar_attach()
499 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
502 error = dmar_init_qi(unit); in dmar_attach()
504 dmar_release_resources(dev, unit); in dmar_attach()
505 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
508 error = dmar_init_irt(unit); in dmar_attach()
510 dmar_release_resources(dev, unit); in dmar_attach()
511 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
518 error = dmar_disable_protected_regions(unit); in dmar_attach()
524 error = iommu_init_busdma(&unit->iommu); in dmar_attach()
526 dmar_release_resources(dev, unit); in dmar_attach()
527 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
532 DMAR_LOCK(unit); in dmar_attach()
533 error = dmar_enable_translation(unit); in dmar_attach()
535 DMAR_UNLOCK(unit); in dmar_attach()
536 dmar_release_resources(dev, unit); in dmar_attach()
537 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
540 DMAR_UNLOCK(unit); in dmar_attach()
704 dmar_match_by_path(struct dmar_unit *unit, int dev_domain, int dev_busno, in dmar_match_by_path() argument
712 dmarh = dmar_find_by_index(unit->iommu.unit); in dmar_match_by_path()
744 struct dmar_unit *unit; in dmar_find_by_scope() local
750 unit = device_get_softc(dmar_devs[i]); in dmar_find_by_scope()
751 if (dmar_match_by_path(unit, dev_domain, dev_busno, dev_path, in dmar_find_by_scope()
753 return (unit); in dmar_find_by_scope()
761 struct dmar_unit *unit; in dmar_find() local
781 unit = device_get_softc(dmar_devs[i]); in dmar_find()
782 if (dmar_match_by_path(unit, dev_domain, dev_busno, in dmar_find()
792 pci_get_function(dev), unit->iommu.unit, banner); in dmar_find()
797 iommu_device_set_iommu_prop(dev, unit->iommu.dev); in dmar_find()
798 return (unit); in dmar_find()
805 struct dmar_unit *unit; in dmar_find_nonpci() local
819 unit = (struct dmar_unit *)device_get_softc(dmar_dev); in dmar_find_nonpci()
842 return (unit); in dmar_find_nonpci()
853 return (unit); in dmar_find_nonpci()
867 struct dmar_unit *unit; in dmar_find_hpet() local
869 unit = dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET, in dmar_find_hpet()
871 if (unit != NULL) in dmar_find_hpet()
872 iommu_device_set_iommu_prop(dev, unit->iommu.dev); in dmar_find_hpet()
873 return (unit); in dmar_find_hpet()
879 struct dmar_unit *unit; in dmar_find_ioapic() local
882 unit = dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid); in dmar_find_ioapic()
883 if (unit != NULL) { in dmar_find_ioapic()
886 iommu_device_set_iommu_prop(apic_dev, unit->iommu.dev); in dmar_find_ioapic()
888 return (unit); in dmar_find_ioapic()
993 struct dmar_unit *unit; in dmar_inst_rmrr_iter() local
1029 iria->dmar->iommu.unit, in dmar_inst_rmrr_iter()
1037 unit = dmar_find_by_scope(resmem->Segment, in dmar_inst_rmrr_iter()
1041 if (iria->dmar != unit) in dmar_inst_rmrr_iter()
1048 unit = dmar_find(dev, false); in dmar_inst_rmrr_iter()
1049 if (iria->dmar != unit) in dmar_inst_rmrr_iter()
1071 dmar_instantiate_rmrr_ctxs(struct iommu_unit *unit) in dmar_instantiate_rmrr_ctxs() argument
1077 dmar = IOMMU2DMAR(unit); in dmar_instantiate_rmrr_ctxs()
1089 dmar->iommu.unit)); in dmar_instantiate_rmrr_ctxs()
1093 dmar->iommu.unit); in dmar_instantiate_rmrr_ctxs()
1098 dmar->iommu.unit); in dmar_instantiate_rmrr_ctxs()
1101 "error %d\n", dmar->iommu.unit, error); in dmar_instantiate_rmrr_ctxs()
1135 struct dmar_unit *unit; in DB_SHOW_COMMAND_FLAGS() local
1183 unit = device_get_softc(dmar_devs[i]); in DB_SHOW_COMMAND_FLAGS()
1184 LIST_FOREACH(domain, &unit->domains, link) { in DB_SHOW_COMMAND_FLAGS()
1186 if (pci_domain == unit->segment && in DB_SHOW_COMMAND_FLAGS()
1204 struct dmar_unit *unit; in dmar_print_one() local
1208 unit = device_get_softc(dmar_devs[idx]); in dmar_print_one()
1209 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->iommu.unit, in dmar_print_one()
1210 unit, dmar_read8(unit, DMAR_RTADDR_REG), in dmar_print_one()
1211 dmar_read4(unit, DMAR_VER_REG)); in dmar_print_one()
1213 (uintmax_t)dmar_read8(unit, DMAR_CAP_REG), in dmar_print_one()
1214 (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG), in dmar_print_one()
1215 dmar_read4(unit, DMAR_GSTS_REG), in dmar_print_one()
1216 dmar_read4(unit, DMAR_FSTS_REG), in dmar_print_one()
1217 dmar_read4(unit, DMAR_FECTL_REG)); in dmar_print_one()
1218 if (unit->ir_enabled) { in dmar_print_one()
1220 unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt); in dmar_print_one()
1223 dmar_read4(unit, DMAR_FEDATA_REG), in dmar_print_one()
1224 dmar_read4(unit, DMAR_FEADDR_REG), in dmar_print_one()
1225 dmar_read4(unit, DMAR_FEUADDR_REG)); in dmar_print_one()
1227 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) { in dmar_print_one()
1228 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16; in dmar_print_one()
1230 (uintmax_t)dmar_read8(unit, frir), in dmar_print_one()
1231 (uintmax_t)dmar_read8(unit, frir + 8)); in dmar_print_one()
1233 if (DMAR_HAS_QI(unit)) { in dmar_print_one()
1235 dmar_read4(unit, DMAR_IEDATA_REG), in dmar_print_one()
1236 dmar_read4(unit, DMAR_IEADDR_REG), in dmar_print_one()
1237 dmar_read4(unit, DMAR_IEUADDR_REG)); in dmar_print_one()
1238 if (unit->qi_enabled) { in dmar_print_one()
1243 (uintmax_t)unit->x86c.inv_queue, in dmar_print_one()
1244 (uintmax_t)dmar_read8(unit, DMAR_IQA_REG), in dmar_print_one()
1245 (uintmax_t)unit->x86c.inv_queue_size, in dmar_print_one()
1246 dmar_read4(unit, DMAR_IQH_REG), in dmar_print_one()
1247 dmar_read4(unit, DMAR_IQT_REG), in dmar_print_one()
1248 unit->x86c.inv_queue_avail, in dmar_print_one()
1249 dmar_read4(unit, DMAR_ICS_REG), in dmar_print_one()
1250 dmar_read4(unit, DMAR_IECTL_REG), in dmar_print_one()
1251 (uintmax_t)unit->x86c.inv_waitd_seq_hw, in dmar_print_one()
1252 &unit->x86c.inv_waitd_seq_hw, in dmar_print_one()
1253 (uintmax_t)unit->x86c.inv_waitd_seq_hw_phys, in dmar_print_one()
1254 unit->x86c.inv_waitd_seq, in dmar_print_one()
1255 unit->x86c.inv_waitd_gen); in dmar_print_one()
1262 LIST_FOREACH(domain, &unit->domains, link) { in dmar_print_one()
1309 dmar_get_x86_common(struct iommu_unit *unit) in dmar_get_x86_common() argument
1313 dmar = IOMMU2DMAR(unit); in dmar_get_x86_common()
1318 dmar_unit_pre_instantiate_ctx(struct iommu_unit *unit) in dmar_unit_pre_instantiate_ctx() argument
1320 dmar_quirks_pre_use(unit); in dmar_unit_pre_instantiate_ctx()
1321 dmar_instantiate_rmrr_ctxs(unit); in dmar_unit_pre_instantiate_ctx()