174 bool dmar_pglvl_supported(struct dmar_unit *unit, int pglvl);
176 int dmar_maxaddr2mgaw(struct dmar_unit *unit, iommu_gaddr_t maxaddr,
180 int calc_am(struct dmar_unit *unit, iommu_gaddr_t base, iommu_gaddr_t size,
182 int dmar_load_root_entry_ptr(struct dmar_unit *unit);
183 int dmar_inv_ctx_glob(struct dmar_unit *unit);
184 int dmar_inv_iotlb_glob(struct dmar_unit *unit);
185 int dmar_flush_write_bufs(struct dmar_unit *unit);
186 void dmar_flush_pte_to_ram(struct dmar_unit *unit, iommu_pte_t *dst);
187 void dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst);
188 void dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst);
189 int dmar_disable_protected_regions(struct dmar_unit *unit);
190 int dmar_enable_translation(struct dmar_unit *unit);
191 int dmar_disable_translation(struct dmar_unit *unit);
192 int dmar_load_irt_ptr(struct dmar_unit *unit);
193 int dmar_enable_ir(struct dmar_unit *unit);
194 int dmar_disable_ir(struct dmar_unit *unit);
201 void dmar_enable_fault_intr(struct iommu_unit *unit);
202 void dmar_disable_fault_intr(struct iommu_unit *unit);
203 int dmar_init_fault_log(struct dmar_unit *unit);
204 void dmar_fini_fault_log(struct dmar_unit *unit);
207 void dmar_enable_qi_intr(struct iommu_unit *unit);
208 void dmar_disable_qi_intr(struct iommu_unit *unit);
209 int dmar_init_qi(struct dmar_unit *unit);
210 void dmar_fini_qi(struct dmar_unit *unit);
215 void dmar_qi_invalidate_ctx_glob_locked(struct dmar_unit *unit);
216 void dmar_qi_invalidate_iotlb_glob_locked(struct dmar_unit *unit);
217 void dmar_qi_invalidate_iec_glob(struct dmar_unit *unit);
218 void dmar_qi_invalidate_iec(struct dmar_unit *unit, u_int start, u_int cnt);
256 int dmar_init_irt(struct dmar_unit *unit);
257 void dmar_fini_irt(struct dmar_unit *unit);
272 dmar_read4(const struct dmar_unit *unit, int reg)  in dmar_read4()  argument
275 	return (bus_read_4(unit->regs, reg));  in dmar_read4()
279 dmar_read8(const struct dmar_unit *unit, int reg)  in dmar_read8()  argument
284 	low = bus_read_4(unit->regs, reg);  in dmar_read8()
285 	high = bus_read_4(unit->regs, reg + 4);  in dmar_read8()
288 	return (bus_read_8(unit->regs, reg));  in dmar_read8()
293 dmar_write4(const struct dmar_unit *unit, int reg, uint32_t val)  in dmar_write4()  argument
297 	    (unit->hw_gcmd & DMAR_GCMD_TE),  in dmar_write4()
298 	    ("dmar%d clearing TE 0x%08x 0x%08x", unit->iommu.unit,  in dmar_write4()
299 	    unit->hw_gcmd, val));  in dmar_write4()
300 	bus_write_4(unit->regs, reg, val);  in dmar_write4()
304 dmar_write8(const struct dmar_unit *unit, int reg, uint64_t val)  in dmar_write8()  argument
313 	bus_write_4(unit->regs, reg, low);  in dmar_write8()
314 	bus_write_4(unit->regs, reg + 4, high);  in dmar_write8()
316 	bus_write_8(unit->regs, reg, val);  in dmar_write8()