103 	re = iommu_map_pgtbl(dmar->ctx_obj, 0, IOMMU_PGF_NOALLOC, &sf);  in dmar_ensure_ctx_page()
122 	ctxp += ctx->context.rid & 0xff;  in dmar_map_ctx_entry()
161 	KASSERT(move || (ctxp->ctx1 == 0 && ctxp->ctx2 == 0),  in ctx_id_entry_init()
162 	    ("dmar%d: initialized ctx entry %d:%d:%d 0x%jx 0x%jx",  in ctx_id_entry_init()
167 	if ((domain->iodom.flags & IOMMU_DOMAIN_IDMAP) != 0 &&  in ctx_id_entry_init()
168 	    (unit->hw_ecap & DMAR_ECAP_PT) != 0) {  in ctx_id_entry_init()
173 		ctx_root = iommu_pgalloc(domain->pgtbl_obj, 0,  in ctx_id_entry_init()
179 		for (i = 0; i <= PCI_BUSMAX; i++) {  in ctx_id_entry_init()
198 	if ((dmar->hw_cap & DMAR_CAP_CM) == 0 && !force)  in dmar_flush_for_ctx_entry()
199 		return (0);  in dmar_flush_for_ctx_entry()
202 		if ((dmar->hw_ecap & DMAR_ECAP_DI) != 0 || force)  in dmar_flush_for_ctx_entry()
204 		return (0);  in dmar_flush_for_ctx_entry()
207 	if (error == 0 && ((dmar->hw_ecap & DMAR_ECAP_DI) != 0 || force))  in dmar_flush_for_ctx_entry()
225 		return (0);  in domain_init_rmrr()
227 	error = 0;  in domain_init_rmrr()
259 			entry->end += IOMMU_PAGE_SIZE * 0x20;  in domain_init_rmrr()
263 		for (i = 0; i < size; i++) {  in domain_init_rmrr()
276 		if (error1 == 0 && entry->end != entry->start) {  in domain_init_rmrr()
282 			if (error1 != 0) {  in domain_init_rmrr()
295 		for (i = 0; i < size; i++)  in domain_init_rmrr()
323 		return (0);  in dmar_reserve_pci_regions()
326 	base = PCI_PPBMEMBASE(0, pci_read_config(root, PCIR_MEMBASE_1, 2));  in dmar_reserve_pci_regions()
327 	limit = PCI_PPBMEMLIMIT(0, pci_read_config(root, PCIR_MEMLIMIT_1, 2));  in dmar_reserve_pci_regions()
329 	if (bootverbose || error != 0)  in dmar_reserve_pci_regions()
332 	if (error != 0)  in dmar_reserve_pci_regions()
337 	if (val != 0 || pci_read_config(root, PCIR_PMLIMITL_1, 2) != 0) {  in dmar_reserve_pci_regions()
346 			base = PCI_PPBMEMBASE(0, val);  in dmar_reserve_pci_regions()
347 			limit = PCI_PPBMEMLIMIT(0,  in dmar_reserve_pci_regions()
352 		if (bootverbose || error != 0)  in dmar_reserve_pci_regions()
355 		if (error != 0)  in dmar_reserve_pci_regions()
391 	if (error != 0)  in dmar_domain_alloc()
400 		if ((dmar->hw_ecap & DMAR_ECAP_PT) == 0) {  in dmar_domain_alloc()
407 		if (error != 0)  in dmar_domain_alloc()
410 		error = iommu_gas_reserve_region(iodom, 0xfee00000,  in dmar_domain_alloc()
411 		    0xfeefffff + 1, &iodom->msi_entry);  in dmar_domain_alloc()
412 		if (error != 0)  in dmar_domain_alloc()
458 	KASSERT(domain->refs > 0,  in dmar_ctx_unlink()
480 	KASSERT(domain->ctx_cnt == 0,  in dmar_domain_destroy()
482 	KASSERT(domain->refs == 0,  in dmar_domain_destroy()
484 	if ((domain->iodom.flags & IOMMU_DOMAIN_GAS_INITED) != 0) {  in dmar_domain_destroy()
489 	if ((domain->iodom.flags & IOMMU_DOMAIN_PGTBL_INITED) != 0) {  in dmar_domain_destroy()
526 	KASSERT(!iommu_is_buswide_ctx(unit, bus) || (slot == 0 && func == 0),  in dmar_get_ctx_for_dev1()
530 	error = 0;  in dmar_get_ctx_for_dev1()
547 			if (error == 0 && dev != NULL)  in dmar_get_ctx_for_dev1()
549 			if (error != 0) {  in dmar_get_ctx_for_dev1()
605 	if (error != 0) {  in dmar_get_ctx_for_dev1()
616 	if (enable && !rmrr_init && (dmar->hw_gcmd & DMAR_GCMD_TE) == 0) {  in dmar_get_ctx_for_dev1()
618 		if (error != 0)  in dmar_get_ctx_for_dev1()
622 		if (error == 0) {  in dmar_get_ctx_for_dev1()
677 		return (0);  in dmar_move_ctx_to_domain()
695 	    domain->domain, (domain->iodom.flags & IOMMU_DOMAIN_IDMAP) != 0 ?  in dmar_move_ctx_to_domain()
720 	KASSERT((domain->iodom.flags & IOMMU_DOMAIN_RMRR) == 0,  in dmar_unref_domain_locked()
752 	KASSERT((ctx->context.flags & IOMMU_CTX_DISABLED) == 0,  in dmar_free_ctx_locked()
779 	KASSERT((ctx->context.flags & IOMMU_CTX_DISABLED) == 0,  in dmar_free_ctx_locked()
787 	ctxp->ctx2 = 0;  in dmar_free_ctx_locked()
790 	if ((dmar->hw_ecap & DMAR_ECAP_DI) != 0) {  in dmar_free_ctx_locked()
869 	return (domain->batch_no++ % iommu_qi_batch_coalesce == 0);  in dmar_domain_unload_emit_wait()
885 		KASSERT((entry->flags & IOMMU_MAP_ENTRY_MAP) != 0,  in dmar_domain_unload()
888 		    cansleep ? IOMMU_PGF_WAITOK : 0);  in dmar_domain_unload()
889 		KASSERT(error == 0, ("unmap %p error %d", domain, error));  in dmar_domain_unload()