Lines Matching +full:irq +full:- +full:device

1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
34  * Values used in determining the allocation of IRQ values among
37  * device interrupt source whether it be a pin on an interrupt
39  * IDT vectors, but all other device interrupts allocate IDT vectors
40  * on demand.  Currently we have 191 IDT vectors available for device
42  * the IRQs are not used, so the total number of IRQ values reserved
45  * The first 16 IRQs (0 - 15) are reserved for ISA IRQs.  Interrupt
46  * pins on I/O APICs for non-ISA interrupts use IRQ values starting at
47  * IRQ 17.  This layout matches the GSI numbering used by ACPI so that
48  * IRQ values returned by ACPI methods such as _CRS can be used
53  * additional range of IRQ values are available for binding to event
101  * An interrupt source.  The upper-layer code uses the PIC methods to
102  * control a given source.  The lower-layer PIC drivers can store additional
133 enum intr_trigger elcr_read_trigger(u_int irq);
135 void	elcr_write_trigger(u_int irq, enum intr_trigger trigger);
155 void	nexus_add_irq(u_long irq);
158 int	msi_map(int irq, uint64_t *addr, uint32_t *data);
160 int	msix_alloc(device_t dev, int *irq);
161 int	msix_release(int irq);