1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
34  * Reference:  Intel Developer's manual v.3 #245472-012
125 	if (device_find_child(parent, "p4tcc", -1) != NULL)  in p4tcc_identify()
157 	sc->dev = dev;  in p4tcc_attach()
158 	sc->set_count = TCC_NUM_SETTINGS;  in p4tcc_attach()
161 	 * On boot, the TCC is usually in Automatic mode where reading the  in p4tcc_attach()
166 	sc->auto_mode = TRUE;  in p4tcc_attach()
169 	 * XXX: After a cursory glance at various Intel specification  in p4tcc_attach()
170 	 * XXX: updates it seems like these tests for errata is bogus.  in p4tcc_attach()
171 	 * XXX: As far as I can tell, the failure mode is benign, in  in p4tcc_attach()
172 	 * XXX: that cpus with no errata will have their bottom two  in p4tcc_attach()
173 	 * XXX: STPCLK# rates disabled, so rather than waste more time  in p4tcc_attach()
174 	 * XXX: hunting down intel docs, just document it and punt. /phk  in p4tcc_attach()
186 		sc->set_count -= 1;  in p4tcc_attach()
199 		sc->set_count -= 2;  in p4tcc_attach()
202 	sc->lowest_val = TCC_NUM_SETTINGS - sc->set_count + 1;  in p4tcc_attach()
226 	 * Before we finish detach, switch to Automatic mode.  in p4tcc_detach()
242 	if (*count < sc->set_count)  in p4tcc_settings()
246 	memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->set_count);  in p4tcc_settings()
248 	for (i = 0; i < sc->set_count; i++, val--) {  in p4tcc_settings()
252 	*count = sc->set_count;  in p4tcc_settings()
270 	 * from [sc->lowest_val .. TCC_NUM_SETTINGS].  in p4tcc_set()
272 	val = set->freq * TCC_NUM_SETTINGS / 10000;  in p4tcc_set()
273 	if (val * 10000 != set->freq * TCC_NUM_SETTINGS ||  in p4tcc_set()
274 	    val < sc->lowest_val || val > TCC_NUM_SETTINGS)  in p4tcc_set()
279 	 * On-Demand bit.  If the new val is < 100%, set it and the On-Demand  in p4tcc_set()
280 	 * bit, otherwise just return to Automatic mode.  in p4tcc_set()
283 	mask = (TCC_NUM_SETTINGS - 1) << TCC_REG_OFFSET;  in p4tcc_set()
290 	 * Record whether we're now in Automatic or On-Demand mode.  We have  in p4tcc_set()
292 	 * Automatic mode (i.e., at 100% or possibly 50%).  Reading bit 4 of  in p4tcc_set()
294 	 * what the current mode.  in p4tcc_set()
297 		sc->auto_mode = FALSE;  in p4tcc_set()
299 		sc->auto_mode = TRUE;  in p4tcc_set()
317 	 * in automatic mode, assume we're at TCC_NUM_SETTINGS (100%).  in p4tcc_get()
319 	 * XXX This is not completely reliable since at high temperatures  in p4tcc_get()
323 	if (!sc->auto_mode) {  in p4tcc_get()
325 		val = (msr >> TCC_REG_OFFSET) & (TCC_NUM_SETTINGS - 1);  in p4tcc_get()
330 	set->freq = TCC_SPEED_PERCENT(val);  in p4tcc_get()
331 	set->dev = dev;  in p4tcc_get()