Lines Matching full:bus_clk
85 #define ID16(MHz, mV, bus_clk) \ argument
86 (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4))
87 #define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk) \ argument
88 ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk)))
91 #define FREQ_INFO_PWR(MHz, mV, bus_clk, mW) \ argument
92 { MHz, mV, ID16(MHz, mV, bus_clk), mW }
93 #define FREQ_INFO(MHz, mV, bus_clk) \ argument
94 FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN)
95 #define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \ argument
96 { CPU_VENDOR_INTEL, ID32(zhi, vhi, zlo, vlo, bus_clk), tab, nitems(tab) }
97 #define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk) \ argument
98 { CPU_VENDOR_CENTAUR, ID32(zhi, vhi, zlo, vlo, bus_clk), tab, nitems(tab) }