Lines Matching +full:- +full:100
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
52 /* Status/control registers (from the IA-32 System Programming Guide). */
86 (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4))
102 static int strict = -1;
106 #define INTEL_BUS_CLK 100
125 * Order Number 252612-003, Table 5.
215 * 2-MB L2 Cache Datasheet", Order Number 302189-008, Table 5.
665 * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants.
666 * Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet.
669 /* 2.00GHz Centaur C7-M 533 Mhz FSB */
680 /* 1.80GHz Centaur C7-M 533 Mhz FSB */
690 /* 1.60GHz Centaur C7-M 533 Mhz FSB */
700 /* 2.00GHz Centaur C7-M 400 Mhz FSB */
701 FREQ_INFO_PWR(2000, 1148, 100, 20000),
702 FREQ_INFO_PWR(1800, 1132, 100, 18000),
703 FREQ_INFO_PWR(1600, 1100, 100, 15000),
704 FREQ_INFO_PWR(1400, 1052, 100, 13000),
705 FREQ_INFO_PWR(1000, 1004, 100, 10000),
706 FREQ_INFO_PWR( 800, 844, 100, 7000),
707 FREQ_INFO_PWR( 600, 844, 100, 6000),
708 FREQ_INFO_PWR( 400, 844, 100, 5000),
711 /* 1.80GHz Centaur C7-M 400 Mhz FSB */
712 FREQ_INFO_PWR(1800, 1148, 100, 18000),
713 FREQ_INFO_PWR(1600, 1100, 100, 15000),
714 FREQ_INFO_PWR(1400, 1052, 100, 13000),
715 FREQ_INFO_PWR(1000, 1004, 100, 10000),
716 FREQ_INFO_PWR( 800, 844, 100, 7000),
717 FREQ_INFO_PWR( 600, 844, 100, 6000),
718 FREQ_INFO_PWR( 400, 844, 100, 5000),
721 /* 1.60GHz Centaur C7-M 400 Mhz FSB */
722 FREQ_INFO_PWR(1600, 1084, 100, 15000),
723 FREQ_INFO_PWR(1400, 1052, 100, 13000),
724 FREQ_INFO_PWR(1000, 1004, 100, 10000),
725 FREQ_INFO_PWR( 800, 844, 100, 7000),
726 FREQ_INFO_PWR( 600, 844, 100, 6000),
727 FREQ_INFO_PWR( 400, 844, 100, 5000),
730 /* 1.50GHz Centaur C7-M 400 Mhz FSB */
731 FREQ_INFO_PWR(1500, 1004, 100, 12000),
732 FREQ_INFO_PWR(1400, 988, 100, 11000),
733 FREQ_INFO_PWR(1000, 940, 100, 9000),
734 FREQ_INFO_PWR( 800, 844, 100, 7000),
735 FREQ_INFO_PWR( 600, 844, 100, 6000),
736 FREQ_INFO_PWR( 400, 844, 100, 5000),
739 /* 1.20GHz Centaur C7-M 400 Mhz FSB */
740 FREQ_INFO_PWR(1200, 860, 100, 7000),
741 FREQ_INFO_PWR(1000, 860, 100, 6000),
742 FREQ_INFO_PWR( 800, 844, 100, 5500),
743 FREQ_INFO_PWR( 600, 844, 100, 5000),
744 FREQ_INFO_PWR( 400, 844, 100, 4000),
748 /* 1.50GHz Centaur C7-M ULV */
749 FREQ_INFO_PWR(1500, 956, 100, 7500),
750 FREQ_INFO_PWR(1400, 940, 100, 6000),
751 FREQ_INFO_PWR(1000, 860, 100, 5000),
752 FREQ_INFO_PWR( 800, 828, 100, 2800),
753 FREQ_INFO_PWR( 600, 796, 100, 2500),
754 FREQ_INFO_PWR( 400, 796, 100, 2000),
757 /* 1.20GHz Centaur C7-M ULV */
758 FREQ_INFO_PWR(1200, 844, 100, 5000),
759 FREQ_INFO_PWR(1000, 844, 100, 4000),
760 FREQ_INFO_PWR( 800, 828, 100, 2800),
761 FREQ_INFO_PWR( 600, 796, 100, 2500),
762 FREQ_INFO_PWR( 400, 796, 100, 2000),
765 /* 1.00GHz Centaur C7-M ULV */
766 FREQ_INFO_PWR(1000, 796, 100, 3500),
767 FREQ_INFO_PWR( 800, 796, 100, 2800),
768 FREQ_INFO_PWR( 600, 796, 100, 2500),
769 FREQ_INFO_PWR( 400, 796, 100, 2000),
772 /* 1.00GHz Centaur C7-M ULV */
773 FREQ_INFO_PWR(1000, 844, 100, 5000),
774 FREQ_INFO_PWR( 800, 796, 100, 2800),
775 FREQ_INFO_PWR( 600, 796, 100, 2500),
776 FREQ_INFO_PWR( 400, 796, 100, 2000),
839 CENTAUR(C7M_794, 2000, 1148, 400, 844, 100),
841 CENTAUR(C7M_784, 1800, 1148, 400, 844, 100),
843 CENTAUR(C7M_764, 1600, 1084, 400, 844, 100),
844 CENTAUR(C7M_754, 1500, 1004, 400, 844, 100),
845 CENTAUR(C7M_775_ULV, 1500, 956, 400, 796, 100),
846 CENTAUR(C7M_771, 1200, 860, 400, 844, 100),
847 CENTAUR(C7M_772_ULV, 1200, 844, 400, 796, 100),
848 CENTAUR(C7M_779_ULV, 1000, 796, 400, 796, 100),
849 CENTAUR(C7M_770_ULV, 1000, 844, 400, 796, 100),
997 sc->dev = dev; in est_attach()
1000 if (strict == -1 && mp_ncpus > 1) in est_attach()
1021 if (sc->acpi_settings || sc->msr_settings) in est_detach()
1022 free(sc->freq_list, M_DEVBUF); in est_detach()
1030 * series) export both legacy SMM IO-based access and direct MSR access
1042 error = est_table_info(dev, msr, &sc->freq_list, &sc->flist_len); in est_get_info()
1044 error = est_acpi_info(dev, &sc->freq_list, &sc->flist_len); in est_get_info()
1046 error = est_msr_info(dev, msr, &sc->freq_list, &sc->flist_len); in est_get_info()
1113 sc->acpi_settings = TRUE; in est_acpi_info()
1134 for (p = ESTprocs; p->id32 != 0; p++) { in est_table_info()
1135 if (p->vendor_id == cpu_vendor_id && p->id32 == id) in est_table_info()
1138 if (p->id32 == 0) in est_table_info()
1142 if (est_get_current(p->freqtab, p->tablen) == NULL) { in est_table_info()
1147 *freqs = p->freqtab; in est_table_info()
1148 *freqslen = p->tablen; in est_table_info()
1157 case 100: in bus_speed_ok()
1232 sc->msr_settings = TRUE; in est_msr_info()
1285 if (f->id16 == id16) in est_get_current()
1288 DELAY(100); in est_get_current()
1305 for (f = sc->freq_list; f < sc->freq_list + sc->flist_len; f++, i++) { in est_settings()
1306 sets[i].freq = f->freq; in est_settings()
1307 sets[i].volts = f->volts; in est_settings()
1308 sets[i].power = f->power; in est_settings()
1325 for (f = sc->freq_list; f < sc->freq_list + sc->flist_len; f++) { in est_set()
1326 if (f->freq == set->freq) in est_set()
1329 if (f->freq == 0) in est_set()
1333 est_set_id16(dev, f->id16, 0); in est_set()
1345 f = est_get_current(sc->freq_list, sc->flist_len); in est_get()
1349 set->freq = f->freq; in est_get()
1350 set->volts = f->volts; in est_get()
1351 set->power = f->power; in est_get()
1352 set->lat = EST_TRANS_LAT; in est_get()
1353 set->dev = dev; in est_get()