57 #define	SFUART_TXDATA			0x00
59 #define	SFUART_RXDATA			0x04
61 #define	SFUART_TXCTRL			0x08
62 #define		SFUART_TXCTRL_ENABLE	0x01
63 #define		SFUART_TXCTRL_NSTOP	0x02
64 #define		SFUART_TXCTRL_TXCNT	0x70000
66 #define	SFUART_RXCTRL			0x0c
67 #define		SFUART_RXCTRL_ENABLE	0x01
68 #define		SFUART_RXCTRL_RXCNT	0x70000
70 #define	SFUART_IRQ_ENABLE		0x10
71 #define		SFUART_IRQ_ENABLE_TXWM	0x01
72 #define		SFUART_IRQ_ENABLE_RXWM	0x02
73 #define	SFUART_IRQ_PENDING		0x14
74 #define		SFUART_IRQ_PENDING_TXWM	0x01
75 #define		SFUART_IRQ_PENDING_RXQM	0x02
76 #define	SFUART_DIV			0x18
77 #define	SFUART_REGS_SIZE		0x1c
93 	return (0);  in sfuart_probe()
102 	uart_setreg(bas, SFUART_IRQ_ENABLE, 0);  in sfuart_init()
107 	reg |= (0 << SFUART_RXCTRL_RXCNT_SHIFT);  in sfuart_init()
128 	    != 0)  in sfuart_putc()
140 	 * we've configured the watermark to be 0 and that interrupts are off  in sfuart_rxready()
145 	    SFUART_IRQ_PENDING_RXQM) != 0);  in sfuart_rxready()
156 	    SFUART_RXDATA_EMPTY) != 0) {  in sfuart_getc()
164 	return (c & 0xff);  in sfuart_getc()
178 	sc->sc_hwiflow = 0;  in sfuart_bus_probe()
179 	sc->sc_hwoflow = 0;  in sfuart_bus_probe()
183 	return (0);  in sfuart_bus_probe()
198 	error = clk_get_by_ofw_index(sc->sc_dev, 0, 0, &sfsc->clk);  in sfuart_bus_attach()
211 	if (error || freq == 0) {  in sfuart_bus_attach()
221 	reg |= (0 << SFUART_RXCTRL_RXCNT_SHIFT);  in sfuart_bus_attach()
231 	return (0);  in sfuart_bus_attach()
244 	uart_setreg(bas, SFUART_RXCTRL, 0);  in sfuart_bus_detach()
245 	uart_setreg(bas, SFUART_TXCTRL, 0);  in sfuart_bus_detach()
248 	uart_setreg(bas, SFUART_IRQ_ENABLE, 0);  in sfuart_bus_detach()
252 	return (0);  in sfuart_bus_detach()
267 		} while ((reg & SFUART_TXDATA_FULL) != 0);  in sfuart_bus_flush()
273 		} while ((reg & SFUART_RXDATA_EMPTY) == 0);  in sfuart_bus_flush()
277 	return (0);  in sfuart_bus_flush()
286 	} while (0)
321 	return (0);  in sfuart_bus_setsig()
338 		if (reg == 0) {  in sfuart_bus_ioctl()
344 		error = 0;  in sfuart_bus_ioctl()
366 	ipend = 0;  in sfuart_bus_ipend()
370 	if ((reg & SFUART_IRQ_PENDING_TXWM) != 0 &&  in sfuart_bus_ipend()
371 	    (ie & SFUART_IRQ_ENABLE_TXWM) != 0) {  in sfuart_bus_ipend()
379 	if ((reg & SFUART_IRQ_PENDING_RXQM) != 0)  in sfuart_bus_ipend()
414 	if (baudrate > 0 && bas->rclk != 0) {  in sfuart_bus_param()
420 	return (0);  in sfuart_bus_param()
433 	while ((reg & SFUART_RXDATA_EMPTY) == 0) {  in sfuart_bus_receive()
439 		uart_rx_put(sc, reg & 0xff);  in sfuart_bus_receive()
446 	return (0);  in sfuart_bus_receive()
463 	for (i = 0; i < sc->sc_txdatasz; i++)  in sfuart_bus_transmit()
470 	return (0);  in sfuart_bus_transmit()
537 	.uc_rclk = 0,
538 	.uc_rshift = 0