Lines Matching +full:0 +full:x38000
57 { SYS_RES_MEMORY, 0, RF_ACTIVE },
90 #define PRCI_PLL_DIVR_MASK 0x3f
91 #define PRCI_PLL_DIVR_SHIFT 0
92 #define PRCI_PLL_DIVF_MASK 0x7fc0
94 #define PRCI_PLL_DIVQ_MASK 0x38000
98 #define PRCI_DEVICES_RESET_N 0x28
118 #define PLL_END PLL(0, NULL, 0)
137 #define DIV_END DIV(0, NULL, NULL, 0, 0)
154 #define GATE_END GATE(0, NULL, NULL, 0)
165 #define FU540_PRCI_CORECLK 0
171 #define FU540_PRCI_COREPLL_CFG0 0x4
172 #define FU540_PRCI_DDRPLL_CFG0 0xC
173 #define FU540_PRCI_GEMGXLPLL_CFG0 0x1C
202 #define FU740_PRCI_CORECLK 0
213 #define FU740_PRCI_COREPLL_CFG0 0x4
214 #define FU740_PRCI_DDRPLL_CFG0 0xC
215 #define FU740_PRCI_PCIEAUX_GATE 0x14
216 #define FU740_PRCI_GEMGXLPLL_CFG0 0x1C
217 #define FU740_PRCI_DVFSCOREPLL_CFG0 0x38
218 #define FU740_PRCI_HFPCLKPLL_CFG0 0x50
219 #define FU740_PRCI_CLTXPLL_CFG0 0x30
220 #define FU740_PRCI_HFPCLK_DIV 0x5C
270 { NULL, 0 },
277 clknode_init_parent_idx(clk, 0); in prci_clk_pll_init()
279 return (0); in prci_clk_pll_init()
318 return (0); in prci_clk_pll_recalc()
335 clknode_init_parent_idx(clk, 0); in prci_clk_div_init()
337 return (0); in prci_clk_div_init()
372 return (0); in prci_clk_div_recalc()
392 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) in prci_probe()
472 if (error != 0 || ncells < 1) { in prci_attach()
480 for (i = 0; i < ncells; i++) { in prci_attach()
481 error = clk_get_by_ofw_index(dev, 0, i, &clk_parent); in prci_attach()
482 if (error != 0) { in prci_attach()
527 clkdef_gate.shift = 0; in prci_attach()
530 clkdef_gate.off_value = 0; in prci_attach()
533 if (error != 0) { in prci_attach()
558 return (0); in prci_attach()
578 return (0); in prci_write_4()
590 return (0); in prci_read_4()
606 return (0); in prci_modify_4()
647 return (0); in prci_reset_assert()
663 *reset = (reg & (1u << id)) == 0; in prci_reset_is_asserted()
666 return (0); in prci_reset_is_asserted()
697 EARLY_DRIVER_MODULE(sifive_prci, simplebus, prci_driver, 0, 0,