Lines Matching +full:64 +full:mb

69 #define	VM_PHYSSEG_MAX		64
89  * An allocation size of 16MB is supported in order to optimize the
91  * at most four TTEs, collectively mapping 16MB of physical memory.
92  * By reducing the number of distinct 16MB "pages" that are used by UMA,
93  * the physical memory allocator reduces the likelihood of both 4MB
94  * page TLB misses and cache misses caused by 4MB page TLB misses.
119  * four-level page tables.  64-bit RISC-V implementations are required to provide
123  * The address space is split into two regions at each end of the 64-bit address
134  * 0xfffffff000000000 - 0xffffffffffffffff    64GB unused
143  * 0xfffffff000000000 - 0xffffffffffffffff    64GB unused
150  * 64 bit address space, mostly just for convenience.
243 #define	ZERO_REGION_SIZE	(64 * 1024)	/* 64KB */