Lines Matching +full:machine +full:- +full:level

1 /*-
2  * Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com>
7  * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
39 #include <machine/atomic.h>
40 #include <machine/cpufunc.h>
41 #include <machine/frame.h>
44 #define	TRAPF_PC(tfp)		((tfp)->tf_sepc)
45 #define	TRAPF_USERMODE(tfp)	(((tfp)->tf_sstatus & SSTATUS_SPP) == 0)
47 #define	cpu_getstack(td)	((td)->td_frame->tf_sp)
48 #define	cpu_setstack(td, sp)	((td)->td_frame->tf_sp = (sp))
60  * Micro-architecture ID register, marchid.
62  * IDs for open-source implementations are allocated globally. Commercial IDs
63  * will have the most-significant bit set.
66 #define	MARCHID_MSB		(1ul << (XLEN - 1))
72  * Open-source marchid values.
74  * https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md
85  * MMU virtual-addressing modes. Support for each level implies the previous,
86  * so Sv48-enabled systems MUST support Sv39, etc.
88 #define	MMU_SV39	0x1	/* 3-level paging */
89 #define	MMU_SV48	0x2	/* 4-level paging */
90 #define	MMU_SV57	0x4	/* 5-level paging */