314 	struct xive_cpu *xive_cpud;  in xive_attach()  local
366 		xive_cpud = DPCPU_ID_PTR(i, xive_cpu_data);  in xive_attach()
367 		xive_cpud->vp = vp_id + vp_block;  in xive_attach()
368 		opal_call(OPAL_XIVE_GET_VP_INFO, xive_cpud->vp, NULL,  in xive_attach()
369 		    vtophys(&xive_cpud->cam), NULL, vtophys(&xive_cpud->chip));  in xive_attach()
371 		xive_cpud->cam = be64toh(xive_cpud->cam);  in xive_attach()
372 		xive_cpud->chip = be64toh(xive_cpud->chip);  in xive_attach()
375 		xive_cpud->queue.q_page = contigmalloc(PAGE_SIZE, M_XIVE,  in xive_attach()
377 		xive_cpud->queue.q_size = 1 << PAGE_SHIFT;  in xive_attach()
378 		xive_cpud->queue.q_mask =  in xive_attach()
379 		    ((xive_cpud->queue.q_size / sizeof(int)) - 1);  in xive_attach()
380 		xive_cpud->queue.q_toggle = 0;  in xive_attach()
381 		xive_cpud->queue.q_index = 0;  in xive_attach()
383 			error = opal_call(OPAL_XIVE_SET_VP_INFO, xive_cpud->vp,  in xive_attach()
387 		    XIVE_PRIORITY, vtophys(xive_cpud->queue.q_page), PAGE_SHIFT,  in xive_attach()
392 			    xive_cpud->chip);  in xive_attach()
400 			xive_init_irq(&xive_cpud->ipi_data, ipi_irq);  in xive_attach()
401 			xive_cpud->ipi_data.vp = vp_id;  in xive_attach()
402 			xive_cpud->ipi_data.lirq = MAX_XIVE_IRQS;  in xive_attach()
404 			    xive_cpud->ipi_data.vp, XIVE_PRIORITY,  in xive_attach()
499 	struct xive_cpu *xive_cpud;  in xive_dispatch()  local
506 	xive_cpud = DPCPU_PTR(xive_cpu_data);  in xive_dispatch()
529 			vector = xive_read_eq(&xive_cpud->queue);  in xive_dispatch()
606 	struct xive_cpu *xive_cpud;  in xive_ipi()  local
608 	xive_cpud = DPCPU_ID_PTR(cpu, xive_cpu_data);  in xive_ipi()
610 	if (xive_cpud->ipi_data.trig_page == 0)  in xive_ipi()
612 	xive_write_mmap8(xive_cpud->ipi_data.trig_page, 0);  in xive_ipi()