Lines Matching +full:qemu +full:- +full:1 +full:- +full:setup
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
9 * 1. Redistributions of source code must retain the above copyright
59 #define XIVE_PRIORITY 7 /* Random non-zero number */
60 #define MAX_XIVE_IRQS (1<<24) /* 24-bit XIRR field */
83 #define TM_QW3_NSR_HE_POOL 1
203 EARLY_DRIVER_MODULE(xive, ofwbus, xive_driver, 0, 0, BUS_PASS_INTERRUPT - 1);
210 static int xive_ipi_vector = -1;
232 * could be the same as the EOI page. Level-sensitive interrupts (LSIs) don't
244 * Additionally, the MMIO region mapped is CPU-sensitive, just like the
245 * per-processor register space (private access) in OpenPIC. In order for a CPU
250 * Queues are pages of memory, sized powers-of-two, that are shared with the
256 * Offset-based read/write interfaces.
262 return (bus_read_2(sc->sc_mem, sc->sc_offset + offset)); in xive_read_2()
269 bus_write_1(sc->sc_mem, sc->sc_offset + offset, val); in xive_write_1()
290 if (!ofw_bus_is_compatible(dev, "ibm,opal-xive-pe")) in xive_probe()
303 if (!ofw_bus_is_compatible(dev, "ibm,opal-xive-vc")) in xics_probe()
325 error = OF_getencprop(phandle, "ibm,xive-provision-page-size", in xive_attach()
326 (pcell_t *)&sc->sc_prov_page_size, sizeof(sc->sc_prov_page_size)); in xive_attach()
328 rid = 1; /* Get the Hypervisor-level register set. */ in xive_attach()
329 sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, in xive_attach()
331 sc->sc_offset = XIVE_TM_QW3_HV; in xive_attach()
333 mtx_init(&sc->sc_mtx, "XIVE", NULL, MTX_DEF); in xive_attach()
335 /* Workaround for qemu single-thread powernv */ in xive_attach()
337 order = 1; in xive_attach()
339 order = fls(mp_maxid + (mp_maxid - 1)) - 1; in xive_attach()
349 } while (1); in xive_attach()
355 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->sc_mem); in xive_attach()
364 vp_id = pcpu_find(i)->pc_hwref; in xive_attach()
367 xive_cpud->vp = vp_id + vp_block; in xive_attach()
368 opal_call(OPAL_XIVE_GET_VP_INFO, xive_cpud->vp, NULL, in xive_attach()
369 vtophys(&xive_cpud->cam), NULL, vtophys(&xive_cpud->chip)); in xive_attach()
371 xive_cpud->cam = be64toh(xive_cpud->cam); in xive_attach()
372 xive_cpud->chip = be64toh(xive_cpud->chip); in xive_attach()
375 xive_cpud->queue.q_page = contigmalloc(PAGE_SIZE, M_XIVE, in xive_attach()
377 xive_cpud->queue.q_size = 1 << PAGE_SHIFT; in xive_attach()
378 xive_cpud->queue.q_mask = in xive_attach()
379 ((xive_cpud->queue.q_size / sizeof(int)) - 1); in xive_attach()
380 xive_cpud->queue.q_toggle = 0; in xive_attach()
381 xive_cpud->queue.q_index = 0; in xive_attach()
383 error = opal_call(OPAL_XIVE_SET_VP_INFO, xive_cpud->vp, in xive_attach()
387 XIVE_PRIORITY, vtophys(xive_cpud->queue.q_page), PAGE_SHIFT, in xive_attach()
392 xive_cpud->chip); in xive_attach()
400 xive_init_irq(&xive_cpud->ipi_data, ipi_irq); in xive_attach()
401 xive_cpud->ipi_data.vp = vp_id; in xive_attach()
402 xive_cpud->ipi_data.lirq = MAX_XIVE_IRQS; in xive_attach()
404 xive_cpud->ipi_data.vp, XIVE_PRIORITY, in xive_attach()
410 1 /* Number of IPIs */, FALSE); in xive_attach()
426 MAX_XIVE_IRQS, 1 /* Number of IPIs */, FALSE); in xics_attach()
467 irqd->vp = pcpu_find(cpu)->pc_hwref; in xive_bind()
468 error = opal_call(OPAL_XIVE_SET_IRQ_CONFIG, irq, irqd->vp, in xive_bind()
469 XIVE_PRIORITY, irqd->lirq); in xive_bind()
481 uint32_t i = be32toh(q->q_page[q->q_index]); in xive_read_eq()
484 if ((i >> 31) == q->q_toggle) in xive_read_eq()
487 q->q_index = (q->q_index + 1) & q->q_mask; in xive_read_eq()
489 if (q->q_index == 0) in xive_read_eq()
490 q->q_toggle ^= 1; in xive_read_eq()
529 vector = xive_read_eq(&xive_cpud->queue); in xive_dispatch()
551 if (xive_ipi_vector == -1) in xive_enable()
562 irqd->lirq = vector; in xive_enable()
573 panic("OPAL_SET_XIVE IRQ %d -> cpu %d failed: %d", irq, in xive_enable()
588 rirq = &cpud->ipi_data; in xive_eoi()
592 if (rirq->flags & OPAL_XIVE_IRQ_STORE_EOI) in xive_eoi()
593 xive_write_mmap8(rirq->eoi_page + XIVE_IRQ_STORE_EOI, 0); in xive_eoi()
594 else if (rirq->flags & OPAL_XIVE_IRQ_LSI) in xive_eoi()
595 xive_read_mmap8(rirq->eoi_page + XIVE_IRQ_LOAD_EOI); in xive_eoi()
597 eoi_val = xive_read_mmap8(rirq->eoi_page + XIVE_IRQ_PQ_00); in xive_eoi()
598 if ((eoi_val & XIVE_IRQ_VAL_Q) && rirq->trig_page != 0) in xive_eoi()
599 xive_write_mmap8(rirq->trig_page, 0); in xive_eoi()
610 if (xive_cpud->ipi_data.trig_page == 0) in xive_ipi()
612 xive_write_mmap8(xive_cpud->ipi_data.trig_page, 0); in xive_ipi()
626 if (!(rirq->flags & OPAL_XIVE_IRQ_LSI)) in xive_mask()
628 xive_read_mmap8(rirq->eoi_page + XIVE_IRQ_PQ_01); in xive_mask()
638 xive_read_mmap8(rirq->eoi_page + XIVE_IRQ_PQ_00); in xive_unmask()
651 case 1: in xive_translate_code()
664 * Setup the current CPU. Called by the BSP at driver attachment, and by each
678 val = bus_read_4(sc->sc_mem, XIVE_TM_QW2_HV_POOL + TM_WORD2); in xive_setup_cpu()
680 bus_read_8(sc->sc_mem, XIVE_TM_SPC_PULL_POOL_CTX); in xive_setup_cpu()
682 bus_write_4(sc->sc_mem, XIVE_TM_QW2_HV_POOL + TM_WORD0, 0xff); in xive_setup_cpu()
683 bus_write_4(sc->sc_mem, XIVE_TM_QW2_HV_POOL + TM_WORD2, in xive_setup_cpu()
684 TM_QW2W2_VP | cpup->cam); in xive_setup_cpu()
686 xive_unmask(root_pic, cpup->ipi_data.girq, &cpup->ipi_data); in xive_setup_cpu()
698 vtophys(&irqd->flags), vtophys(&eoi_phys), in xive_init_irq()
700 vtophys(&irqd->chip)); in xive_init_irq()
702 irqd->flags = be64toh(irqd->flags); in xive_init_irq()
706 irqd->chip = be32toh(irqd->chip); in xive_init_irq()
708 irqd->girq = irq; in xive_init_irq()
709 irqd->esb_size = 1 << esb_shift; in xive_init_irq()
710 irqd->eoi_page = (vm_offset_t)pmap_mapdev(eoi_phys, irqd->esb_size); in xive_init_irq()
713 irqd->trig_page = irqd->eoi_page; in xive_init_irq()
715 irqd->trig_page = (vm_offset_t)pmap_mapdev(trig_phys, in xive_init_irq()
716 irqd->esb_size); in xive_init_irq()
718 irqd->trig_page = 0; in xive_init_irq()
720 opal_call(OPAL_XIVE_GET_IRQ_CONFIG, irq, vtophys(&irqd->vp), in xive_init_irq()
721 vtophys(&irqd->prio), vtophys(&irqd->lirq)); in xive_init_irq()
723 irqd->vp = be64toh(irqd->vp); in xive_init_irq()
724 irqd->prio = be64toh(irqd->prio); in xive_init_irq()
725 irqd->lirq = be32toh(irqd->lirq); in xive_init_irq()
752 prov_page = contigmalloc(sc->sc_prov_page_size, M_XIVE, 0, in xive_provision_page()
754 sc->sc_prov_page_size, sc->sc_prov_page_size); in xive_provision_page()
756 error = opal_call(OPAL_XIVE_DONATE_PAGE, -1, in xive_provision_page()