49 dbdma_phys_callback(void *chan, bus_dma_segment_t *segs, int nsegs, int error)  in dbdma_phys_callback()  argument
51 	dbdma_channel_t *channel = (dbdma_channel_t *)(chan);  in dbdma_phys_callback()
59     bus_dma_tag_t parent_dma, int slots, dbdma_channel_t **chan)  in dbdma_allocate_channel()  argument
64 	channel = *chan = malloc(sizeof(struct dbdma_channel), M_DBDMA,   in dbdma_allocate_channel()
92 dbdma_resize_channel(dbdma_channel_t *chan, int newslots)  in dbdma_resize_channel()  argument
98 	chan->sc_nslots = newslots;  in dbdma_resize_channel()
103 dbdma_free_channel(dbdma_channel_t *chan)  in dbdma_free_channel()  argument
106 	dbdma_stop(chan);  in dbdma_free_channel()
108 	bus_dmamem_free(chan->sc_dmatag, chan->sc_slots, chan->sc_dmamap);  in dbdma_free_channel()
109 	bus_dma_tag_destroy(chan->sc_dmatag);  in dbdma_free_channel()
111 	free(chan, M_DBDMA);  in dbdma_free_channel()
117 dbdma_get_cmd_status(dbdma_channel_t *chan, int slot)  in dbdma_get_cmd_status()  argument
120 	bus_dmamap_sync(chan->sc_dmatag, chan->sc_dmamap, BUS_DMASYNC_POSTREAD);  in dbdma_get_cmd_status()
126 	return (le16toh(chan->sc_slots[slot].resCount));  in dbdma_get_cmd_status()
130 dbdma_clear_cmd_status(dbdma_channel_t *chan, int slot)  in dbdma_clear_cmd_status()  argument
133 	chan->sc_slots[slot].resCount = 0;  in dbdma_clear_cmd_status()
137 dbdma_get_residuals(dbdma_channel_t *chan, int slot)  in dbdma_get_residuals()  argument
140 	bus_dmamap_sync(chan->sc_dmatag, chan->sc_dmamap, BUS_DMASYNC_POSTREAD);  in dbdma_get_residuals()
142 	return (le16toh(chan->sc_slots[slot].xferStatus));  in dbdma_get_residuals()
146 dbdma_reset(dbdma_channel_t *chan)  in dbdma_reset()  argument
149 	dbdma_stop(chan);  in dbdma_reset()
150 	dbdma_set_current_cmd(chan, 0);  in dbdma_reset()
151 	dbdma_run(chan);  in dbdma_reset()
155 dbdma_run(dbdma_channel_t *chan)  in dbdma_run()  argument
164 	dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);  in dbdma_run()
168 dbdma_pause(dbdma_channel_t *chan)  in dbdma_pause()  argument
176 	dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);  in dbdma_pause()
180 dbdma_wake(dbdma_channel_t *chan)  in dbdma_wake()  argument
189 	dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);  in dbdma_wake()
193 dbdma_stop(dbdma_channel_t *chan)  in dbdma_stop()  argument
200 	dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);  in dbdma_stop()
202 	while (dbdma_read_reg(chan, CHAN_STATUS_REG) & DBDMA_STATUS_ACTIVE)  in dbdma_stop()
207 dbdma_set_current_cmd(dbdma_channel_t *chan, int slot)  in dbdma_set_current_cmd()  argument
211 	cmd = chan->sc_slots_pa + slot * sizeof(struct dbdma_command);  in dbdma_set_current_cmd()
212 	dbdma_write_reg(chan, CHAN_CMDPTR, cmd);  in dbdma_set_current_cmd()
216 dbdma_get_chan_status(dbdma_channel_t *chan)  in dbdma_get_chan_status()  argument
220 	status_reg = dbdma_read_reg(chan, CHAN_STATUS_REG);  in dbdma_get_chan_status()
225 dbdma_get_device_status(dbdma_channel_t *chan)  in dbdma_get_device_status()  argument
227 	return (dbdma_get_chan_status(chan) & 0x00ff);  in dbdma_get_device_status()
231 dbdma_set_device_status(dbdma_channel_t *chan, uint8_t mask, uint8_t value)  in dbdma_set_device_status()  argument
239 	dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);  in dbdma_set_device_status()
243 dbdma_set_interrupt_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val)  in dbdma_set_interrupt_selector()  argument
251 	dbdma_write_reg(chan, CHAN_INTR_SELECT, intr_select);  in dbdma_set_interrupt_selector()
255 dbdma_set_branch_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val)  in dbdma_set_branch_selector()  argument
263 	dbdma_write_reg(chan, CHAN_BRANCH_SELECT, br_select);  in dbdma_set_branch_selector()
267 dbdma_set_wait_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val)  in dbdma_set_wait_selector()  argument
274 	dbdma_write_reg(chan, CHAN_WAIT_SELECT, wait_select);  in dbdma_set_wait_selector()
278 dbdma_insert_command(dbdma_channel_t *chan, int slot, int command, int stream,  in dbdma_insert_command()  argument
294 		cmd.cmdDep = chan->sc_slots_pa +   in dbdma_insert_command()
311 	chan->sc_slots[slot] = cmd;  in dbdma_insert_command()
315 dbdma_insert_stop(dbdma_channel_t *chan, int slot)  in dbdma_insert_stop()  argument
318 	dbdma_insert_command(chan, slot, DBDMA_STOP, 0, 0, 0, DBDMA_NEVER,  in dbdma_insert_stop()
323 dbdma_insert_nop(dbdma_channel_t *chan, int slot)  in dbdma_insert_nop()  argument
326 	dbdma_insert_command(chan, slot, DBDMA_NOP, 0, 0, 0, DBDMA_NEVER,  in dbdma_insert_nop()
331 dbdma_insert_branch(dbdma_channel_t *chan, int slot, int to_slot)  in dbdma_insert_branch()  argument
334 	dbdma_insert_command(chan, slot, DBDMA_NOP, 0, 0, 0, DBDMA_NEVER,  in dbdma_insert_branch()
339 dbdma_sync_commands(dbdma_channel_t *chan, bus_dmasync_op_t op)  in dbdma_sync_commands()  argument
342 	bus_dmamap_sync(chan->sc_dmatag, chan->sc_dmamap, op);  in dbdma_sync_commands()
346 dbdma_save_state(dbdma_channel_t *chan)  in dbdma_save_state()  argument
349 	chan->sc_saved_regs[0] = dbdma_read_reg(chan, CHAN_CMDPTR);  in dbdma_save_state()
350 	chan->sc_saved_regs[1] = dbdma_read_reg(chan, CHAN_CMDPTR_HI);  in dbdma_save_state()
351 	chan->sc_saved_regs[2] = dbdma_read_reg(chan, CHAN_INTR_SELECT);  in dbdma_save_state()
352 	chan->sc_saved_regs[3] = dbdma_read_reg(chan, CHAN_BRANCH_SELECT);  in dbdma_save_state()
353 	chan->sc_saved_regs[4] = dbdma_read_reg(chan, CHAN_WAIT_SELECT);  in dbdma_save_state()
355 	dbdma_stop(chan);  in dbdma_save_state()
359 dbdma_restore_state(dbdma_channel_t *chan)  in dbdma_restore_state()  argument
362 	dbdma_wake(chan);  in dbdma_restore_state()
363 	dbdma_write_reg(chan, CHAN_CMDPTR, chan->sc_saved_regs[0]);  in dbdma_restore_state()
364 	dbdma_write_reg(chan, CHAN_CMDPTR_HI, chan->sc_saved_regs[1]);  in dbdma_restore_state()
365 	dbdma_write_reg(chan, CHAN_INTR_SELECT, chan->sc_saved_regs[2]);  in dbdma_restore_state()
366 	dbdma_write_reg(chan, CHAN_BRANCH_SELECT, chan->sc_saved_regs[3]);  in dbdma_restore_state()
367 	dbdma_write_reg(chan, CHAN_WAIT_SELECT, chan->sc_saved_regs[4]);  in dbdma_restore_state()
371 dbdma_read_reg(dbdma_channel_t *chan, u_int offset)  in dbdma_read_reg()  argument
374 	return (bus_read_4(chan->sc_regs, chan->sc_off + offset));  in dbdma_read_reg()
378 dbdma_write_reg(dbdma_channel_t *chan, u_int offset, uint32_t val)  in dbdma_write_reg()  argument
381 	bus_write_4(chan->sc_regs, chan->sc_off + offset, val);  in dbdma_write_reg()