72 	struct resource *sc_memr;  member
147 	sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,  in atibl_attach()
149 	if (sc->sc_memr == NULL) {  in atibl_attach()
169 	bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, (reg & 0x3f));  in atibl_pll_rreg()
170 	(void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);  in atibl_pll_rreg()
171 	(void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL);  in atibl_pll_rreg()
173 	data = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);  in atibl_pll_rreg()
176 	save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX);  in atibl_pll_rreg()
178 	bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, tmp);  in atibl_pll_rreg()
179 	tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);  in atibl_pll_rreg()
180 	bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, save);  in atibl_pll_rreg()
190 	bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX,  in atibl_pll_wreg()
192 	(void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);  in atibl_pll_wreg()
193 	(void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL);  in atibl_pll_wreg()
195 	bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA, val);  in atibl_pll_wreg()
199 	save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX);  in atibl_pll_wreg()
201 	bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, tmp);  in atibl_pll_wreg()
202 	tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);  in atibl_pll_wreg()
203 	bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, save);  in atibl_pll_wreg()
220 	lvds_gen_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL);  in atibl_setlevel()
224 		disp_pwr_reg = bus_read_4(sc->sc_memr, RADEON_DISP_PWR_MAN);  in atibl_setlevel()
226 		bus_write_4(sc->sc_memr, RADEON_DISP_PWR_MAN, disp_pwr_reg);  in atibl_setlevel()
227 		lvds_pll_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL);  in atibl_setlevel()
229 		bus_write_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);  in atibl_setlevel()
231 		bus_write_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);  in atibl_setlevel()
242 		bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);  in atibl_setlevel()
249 		bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);  in atibl_setlevel()
252 		bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);  in atibl_setlevel()
267 	lvds_gen_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL);  in atibl_getlevel()