Lines Matching +full:0 +full:x1002
43 #define PCI_VENDOR_ID_ATI 0x1002
47 #define RADEON_LVDS_GEN_CNTL 0x02d0
48 #define RADEON_LVDS_ON (1 << 0)
55 #define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8)
59 #define RADEON_LVDS_PLL_CNTL 0x02d4
62 #define RADEON_PIXCLKS_CNTL 0x002d
64 #define RADEON_DISP_PWR_MAN 0x0d08
66 #define RADEON_CLOCK_CNTL_DATA 0x000c
67 #define RADEON_CLOCK_CNTL_INDEX 0x0008
69 #define RADEON_CRTC_GEN_CNTL 0x0050
92 {0, 0},
101 DRIVER_MODULE(atibl, vgapci, atibl_driver, 0, 0);
123 if (OF_getprop(handle, "backlight-control", &control, sizeof(control)) < 0) in atibl_probe()
126 if (strcmp(control, "ati") != 0 && in atibl_probe()
127 (strcmp(control, "mnca") != 0 || in atibl_probe()
128 pci_get_vendor(device_get_parent(dev)) != 0x1002)) in atibl_probe()
133 return (0); in atibl_probe()
146 rid = 0x18; /* BAR[2], for the MMIO register */ in atibl_attach()
158 "level", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, in atibl_attach()
159 atibl_sysctl, "I", "Backlight level (0-100)"); in atibl_attach()
161 return (0); in atibl_attach()
169 bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, (reg & 0x3f)); in atibl_pll_rreg()
177 tmp = save & (~0x3f | RADEON_PLL_WR_EN); in atibl_pll_rreg()
191 ((reg & 0x3f) | RADEON_PLL_WR_EN)); in atibl_pll_wreg()
200 tmp = save & (~0x3f | RADEON_PLL_WR_EN); in atibl_pll_wreg()
217 if (newlevel < 0) in atibl_setlevel()
218 newlevel = 0; in atibl_setlevel()
222 if (newlevel > 0) { in atibl_setlevel()
258 return (0); in atibl_setlevel()
271 if (level != 0) in atibl_getlevel()
285 atibl_setlevel(sc, 0); in atibl_suspend()
287 return (0); in atibl_suspend()
299 return (0); in atibl_resume()
312 error = sysctl_handle_int(oidp, &newlevel, 0, req); in atibl_sysctl()