Lines Matching defs:sc_memr

72 	struct resource *sc_memr;
147 	sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
149 	if (sc->sc_memr == NULL) {
169 	bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, (reg & 0x3f));
170 	(void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
171 	(void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL);
173 	data = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
176 	save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX);
178 	bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, tmp);
179 	tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
180 	bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, save);
190 	bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX,
192 	(void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
193 	(void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL);
195 	bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA, val);
199 	save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX);
201 	bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, tmp);
202 	tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
203 	bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, save);
220 	lvds_gen_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL);
224 		disp_pwr_reg = bus_read_4(sc->sc_memr, RADEON_DISP_PWR_MAN);
226 		bus_write_4(sc->sc_memr, RADEON_DISP_PWR_MAN, disp_pwr_reg);
227 		lvds_pll_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL);
229 		bus_write_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
231 		bus_write_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
242 		bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
249 		bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
252 		bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
267 	lvds_gen_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL);