1 /*-
2  * SPDX-License-Identifier: BSD-3-Clause
4  * Copyright 2006-2007 by Juniper Networks.
94 #define	REG_PITAR(n)	(0x0e00 - 0x20 * (n))
95 #define	REG_PIWBAR(n)	(0x0e08 - 0x20 * (n))
96 #define	REG_PIWBEAR(n)	(0x0e0c - 0x20 * (n))
97 #define	REG_PIWAR(n)	(0x0e10 - 0x20 * (n))
138 #define	FSL_NUM_MSIS	256	/* 8 registers of 32 bits (8 hardware IRQs) */
139 #define	PCI_SLOT_FIRST	0x1	/* used to be 0x11 but qemu-ppce500 starts from 0x1 */
163 	uint8_t		sc_pcie_capreg;		/* PCI-E Capability Reg Set */
224     int count, int maxcount, int *irqs);
226     int count, int *irqs);
272 	err_reg = bus_space_read_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR);  in fsl_pcib_err_intr()
284 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, clear_reg);  in fsl_pcib_err_intr()
295 	if (!(ofw_bus_is_compatible(dev, "fsl,mpc8540-pci") ||  in fsl_pcib_probe()
296 	    ofw_bus_is_compatible(dev, "fsl,mpc8540-pcie") ||  in fsl_pcib_probe()
297 	    ofw_bus_is_compatible(dev, "fsl,mpc8548-pcie") ||  in fsl_pcib_probe()
298 	    ofw_bus_is_compatible(dev, "fsl,p5020-pcie") ||  in fsl_pcib_probe()
299 	    ofw_bus_is_compatible(dev, "fsl,p5040-pcie") ||  in fsl_pcib_probe()
300 	    ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.2") ||  in fsl_pcib_probe()
301 	    ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.4") ||  in fsl_pcib_probe()
302 	    ofw_bus_is_compatible(dev, "fsl,qoriq-pcie")))  in fsl_pcib_probe()
305 	device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller");  in fsl_pcib_probe()
319 	sc->sc_dev = dev;  in fsl_pcib_attach()
321 	sc->sc_rid = 0;  in fsl_pcib_attach()
322 	sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,  in fsl_pcib_attach()
324 	if (sc->sc_res == NULL) {  in fsl_pcib_attach()
325 		device_printf(dev, "could not map I/O memory\n");  in fsl_pcib_attach()
328 	sc->sc_bst = rman_get_bustag(sc->sc_res);  in fsl_pcib_attach()
329 	sc->sc_bsh = rman_get_bushandle(sc->sc_res);  in fsl_pcib_attach()
330 	sc->sc_busnr = 0;  in fsl_pcib_attach()
332 	ipreg = bus_read_4(sc->sc_res, REG_PEX_IP_BLK_REV1);  in fsl_pcib_attach()
333 	sc->sc_ip_min = (ipreg & IP_MN_M) >> IP_MN_S;  in fsl_pcib_attach()
334 	sc->sc_ip_maj = (ipreg & IP_MJ_M) >> IP_MJ_S;  in fsl_pcib_attach()
335 	mtx_init(&sc->sc_cfg_mtx, "pcicfg", NULL, MTX_SPIN);  in fsl_pcib_attach()
348 			sc->sc_pcie = 1;  in fsl_pcib_attach()
349 			sc->sc_pcie_capreg = capptr;  in fsl_pcib_attach()
380 		brctl = fsl_pcib_read_config(sc->sc_dev, 0, 0, 0,  in fsl_pcib_attach()
383 		fsl_pcib_write_config(sc->sc_dev, 0, 0, 0,  in fsl_pcib_attach()
387 		fsl_pcib_write_config(sc->sc_dev, 0, 0, 0,  in fsl_pcib_attach()
392 	if (sc->sc_pcie) {  in fsl_pcib_attach()
404 	sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,  in fsl_pcib_attach()
406 	if (sc->sc_irq_res == NULL) {  in fsl_pcib_attach()
417 	error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,  in fsl_pcib_attach()
418 	    NULL, fsl_pcib_err_intr, dev, &sc->sc_ih);  in fsl_pcib_attach()
421 		sc->sc_ih = NULL;  in fsl_pcib_attach()
450 	if (sc->sc_pcie)  in fsl_pcib_cfgread()
453 	mtx_lock_spin(&sc->sc_cfg_mtx);  in fsl_pcib_cfgread()
454 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);  in fsl_pcib_cfgread()
458 		data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,  in fsl_pcib_cfgread()
462 		data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,  in fsl_pcib_cfgread()
466 		data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,  in fsl_pcib_cfgread()
473 	mtx_unlock_spin(&sc->sc_cfg_mtx);  in fsl_pcib_cfgread()
488 	if (sc->sc_pcie)  in fsl_pcib_cfgwrite()
491 	mtx_lock_spin(&sc->sc_cfg_mtx);  in fsl_pcib_cfgwrite()
492 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);  in fsl_pcib_cfgwrite()
496 		bus_space_write_1(sc->sc_bst, sc->sc_bsh,  in fsl_pcib_cfgwrite()
500 		bus_space_write_2(sc->sc_bst, sc->sc_bsh,  in fsl_pcib_cfgwrite()
504 		bus_space_write_4(sc->sc_bst, sc->sc_bsh,  in fsl_pcib_cfgwrite()
508 	mtx_unlock_spin(&sc->sc_cfg_mtx);  in fsl_pcib_cfgwrite()
517 #define RD(o)	bus_space_read_4(sc->sc_bst, sc->sc_bsh, o)
546 	return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX);  in fsl_pcib_maxslots()
555 	if (bus == sc->sc_busnr && !sc->sc_pcie &&  in fsl_pcib_read_config()
568 	if (bus == sc->sc_busnr && !sc->sc_pcie &&  in fsl_pcib_write_config()
585 	case -1:  in fsl_pcib_inbound()
589 		attr |= (ffsl(size) - 2);  in fsl_pcib_inbound()
597 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar);  in fsl_pcib_inbound()
598 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0);  in fsl_pcib_inbound()
599 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar);  in fsl_pcib_inbound()
600 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr);  in fsl_pcib_inbound()
611 		attr = 0x80044000 | (ffsll(size) - 2);  in fsl_pcib_outbound()
614 		attr = 0x80088000 | (ffsll(size) - 2);  in fsl_pcib_outbound()
623 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar);  in fsl_pcib_outbound()
624 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0);  in fsl_pcib_outbound()
625 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar);  in fsl_pcib_outbound()
626 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr);  in fsl_pcib_outbound()
641 	if (sc->sc_pcie) {  in fsl_pcib_err_init()
643 		bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER,  in fsl_pcib_err_init()
645 		bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR,  in fsl_pcib_err_init()
647 		bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR,  in fsl_pcib_err_init()
651 		    sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2);  in fsl_pcib_err_init()
654 			    sc->sc_pcie_capreg + PCIER_DEVICE_STA,  in fsl_pcib_err_init()
659 		bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN,  in fsl_pcib_err_init()
664 		    sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4);  in fsl_pcib_err_init()
668 		    sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4);  in fsl_pcib_err_init()
684 	mtx_destroy(&sc->sc_cfg_mtx);  in fsl_pcib_detach()
695 	dev = sc->sc_dev;  in fsl_pcib_decode_win()
697 	fsl_pcib_outbound(sc, 0, -1, 0, 0, 0);  in fsl_pcib_decode_win()
702 	error = law_pci_target(sc->sc_res, &sc->sc_iomem_target,  in fsl_pcib_decode_win()
703 	    &sc->sc_ioport_target);  in fsl_pcib_decode_win()
709 	for (i = 0; i < sc->pci_sc.sc_nrange; i++) {  in fsl_pcib_decode_win()
710 		switch (sc->pci_sc.sc_range[i].pci_hi &  in fsl_pcib_decode_win()
715 			trgt = sc->sc_ioport_target;  in fsl_pcib_decode_win()
717 			    sc->pci_sc.sc_range[i].host,  in fsl_pcib_decode_win()
718 			    sc->pci_sc.sc_range[i].size,  in fsl_pcib_decode_win()
719 			    sc->pci_sc.sc_range[i].pci);  in fsl_pcib_decode_win()
720 			sc->sc_ioport_start = sc->pci_sc.sc_range[i].pci;  in fsl_pcib_decode_win()
721 			sc->sc_ioport_end = sc->pci_sc.sc_range[i].pci +  in fsl_pcib_decode_win()
722 			    sc->pci_sc.sc_range[i].size - 1;  in fsl_pcib_decode_win()
726 			trgt = sc->sc_iomem_target;  in fsl_pcib_decode_win()
728 			    sc->pci_sc.sc_range[i].host,  in fsl_pcib_decode_win()
729 			    sc->pci_sc.sc_range[i].size,  in fsl_pcib_decode_win()
730 			    sc->pci_sc.sc_range[i].pci);  in fsl_pcib_decode_win()
731 			sc->sc_iomem_start = sc->pci_sc.sc_range[i].pci;  in fsl_pcib_decode_win()
732 			sc->sc_iomem_end = sc->pci_sc.sc_range[i].pci +  in fsl_pcib_decode_win()
733 			    sc->pci_sc.sc_range[i].size - 1;  in fsl_pcib_decode_win()
736 			panic("Unknown range type %#x\n",  in fsl_pcib_decode_win()
737 			    sc->pci_sc.sc_range[i].pci_hi &  in fsl_pcib_decode_win()
740 		error = law_enable(trgt, sc->pci_sc.sc_range[i].host,  in fsl_pcib_decode_win()
741 		    sc->pci_sc.sc_range[i].size);  in fsl_pcib_decode_win()
743 			device_printf(dev, "could not program LAW for range "  in fsl_pcib_decode_win()
752 	fsl_pcib_outbound(sc, 3, -1, 0, 0, 0);  in fsl_pcib_decode_win()
753 	fsl_pcib_outbound(sc, 4, -1, 0, 0, 0);  in fsl_pcib_decode_win()
755 	fsl_pcib_inbound(sc, 1, -1, 0, 0, 0);  in fsl_pcib_decode_win()
756 	fsl_pcib_inbound(sc, 2, -1, 0, 0, 0);  in fsl_pcib_decode_win()
760 	/* Direct-map the CCSR for MSIs. */  in fsl_pcib_decode_win()
763 	if (sc->sc_ip_maj >= 2)  in fsl_pcib_decode_win()
774     int count, int maxcount, int *irqs)  in fsl_pcib_alloc_msi()  argument
789 		irqs[i] = start + i;  in fsl_pcib_alloc_msi()
795     int count, int *irqs)  in fsl_pcib_release_msi()  argument
800 	vmem_xfree(msi_vmem, irqs[0], count);  in fsl_pcib_release_msi()
820 		if (irq >= mp->irq_base && irq < mp->irq_base + FSL_NUM_MSIS)  in fsl_pcib_map_msi()
828 	*addr = ccsrbar_pa + mp->target;  in fsl_pcib_map_msi()
835  * on the CCSR.  Since rman doesn't permit overlapping or sub-ranges between
868 	reg = ccsr_read4(ccsrbar_va + data->reg);  in fsl_msi_intr_filter()
872 			powerpc_dispatch_intr(data->vectors[i], NULL);  in fsl_msi_intr_filter()
883 	if (!ofw_bus_is_compatible(dev, "fsl,mpic-msi"))  in fsl_msi_probe()
904 	sc->sc_base = bus_get_resource_start(dev, SYS_RES_MEMORY, 0);  in fsl_msi_attach()
905 	sc->sc_map.target = bus_get_resource_start(dev, SYS_RES_MEMORY, 1);  in fsl_msi_attach()
907 	if (sc->sc_map.target == 0)  in fsl_msi_attach()
908 		sc->sc_map.target = sc->sc_base + FSL_MSI_TARGET;  in fsl_msi_attach()
911 		irq = &sc->sc_msi_irq[i];  in fsl_msi_attach()
912 		irq->irq = i;  in fsl_msi_attach()
913 		irq->reg = sc->sc_base + 16 * i;  in fsl_msi_attach()
914 		irq->res = bus_alloc_resource_any(dev, SYS_RES_IRQ,  in fsl_msi_attach()
915 		    &irq->irq, RF_ACTIVE);  in fsl_msi_attach()
916 		bus_setup_intr(dev, irq->res, INTR_TYPE_MISC | INTR_MPSAFE,  in fsl_msi_attach()
917 		    fsl_msi_intr_filter, NULL, irq, &irq->cookie);  in fsl_msi_attach()
919 	sc->sc_map.irq_base = powerpc_register_pic(dev, ofw_bus_get_node(dev),  in fsl_msi_attach()
923 	vmem_add(msi_vmem, sc->sc_map.irq_base, FSL_NUM_MSIS, M_WAITOK);  in fsl_msi_attach()
925 	SLIST_INSERT_HEAD(&fsl_msis, &sc->sc_map, slist);  in fsl_msi_attach()
938 	irqd = &sc->sc_msi_irq[irq / FSL_NUM_MSI_PER_IRQ];  in fsl_msi_enable()
939 	irqd->vectors[irq % FSL_NUM_MSI_PER_IRQ] = vector;  in fsl_msi_enable()