Lines Matching +full:0 +full:x0c10
77 #define REG_CFG_ADDR 0x0000
78 #define CONFIG_ACCESS_ENABLE 0x80000000
80 #define REG_CFG_DATA 0x0004
81 #define REG_INT_ACK 0x0008
83 #define REG_PEX_IP_BLK_REV1 0x0bf8
84 #define IP_MJ_M 0x0000ff00
86 #define IP_MN_M 0x000000ff
87 #define IP_MN_S 0
89 #define REG_POTAR(n) (0x0c00 + 0x20 * (n))
90 #define REG_POTEAR(n) (0x0c04 + 0x20 * (n))
91 #define REG_POWBAR(n) (0x0c08 + 0x20 * (n))
92 #define REG_POWAR(n) (0x0c10 + 0x20 * (n))
94 #define REG_PITAR(n) (0x0e00 - 0x20 * (n))
95 #define REG_PIWBAR(n) (0x0e08 - 0x20 * (n))
96 #define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n))
97 #define REG_PIWAR(n) (0x0e10 - 0x20 * (n))
98 #define PIWAR_EN 0x80000000
99 #define PIWAR_PF 0x40000000
100 #define PIWAR_TRGT_M 0x00f00000
102 #define PIWAR_TRGT_CCSR 0xe
103 #define PIWAR_TRGT_LOCAL 0xf
105 #define REG_PEX_MES_DR 0x0020
106 #define REG_PEX_MES_IER 0x0028
107 #define REG_PEX_ERR_DR 0x0e00
108 #define REG_PEX_ERR_EN 0x0e08
110 #define REG_PEX_ERR_DR 0x0e00
111 #define REG_PEX_ERR_DR_ME 0x80000000
112 #define REG_PEX_ERR_DR_PCT 0x800000
113 #define REG_PEX_ERR_DR_PAT 0x400000
114 #define REG_PEX_ERR_DR_PCAC 0x200000
115 #define REG_PEX_ERR_DR_PNM 0x100000
116 #define REG_PEX_ERR_DR_CDNSC 0x80000
117 #define REG_PEX_ERR_DR_CRSNC 0x40000
118 #define REG_PEX_ERR_DR_ICCA 0x20000
119 #define REG_PEX_ERR_DR_IACA 0x10000
120 #define REG_PEX_ERR_DR_CRST 0x8000
121 #define REG_PEX_ERR_DR_MIS 0x4000
122 #define REG_PEX_ERR_DR_IOIS 0x2000
123 #define REG_PEX_ERR_DR_CIS 0x1000
124 #define REG_PEX_ERR_DR_CIEP 0x800
125 #define REG_PEX_ERR_DR_IOIEP 0x400
126 #define REG_PEX_ERR_DR_OAC 0x200
127 #define REG_PEX_ERR_DR_IOIA 0x100
128 #define REG_PEX_ERR_DR_IMBA 0x80
129 #define REG_PEX_ERR_DR_IIOBA 0x40
130 #define REG_PEX_ERR_DR_LDDE 0x20
131 #define REG_PEX_ERR_EN 0x0e08
133 #define PCIR_LTSSM 0x404
134 #define LTSSM_STAT_L0 0x16
139 #define PCI_SLOT_FIRST 0x1 /* used to be 0x11 but qemu-ppce500 starts from 0x1 */
258 EARLY_DRIVER_MODULE(pcib, ofwbus, fsl_pcib_driver, 0, 0, BUS_PASS_BUS);
271 clear_reg = 0; in fsl_pcib_err_intr()
275 for (i = 0; i < sizeof(pci_err)/sizeof(struct fsl_pcib_err_dr); i++) { in fsl_pcib_err_intr()
292 strcmp(ofw_bus_get_type(dev), "pci") != 0) in fsl_pcib_probe()
321 sc->sc_rid = 0; in fsl_pcib_attach()
330 sc->sc_busnr = 0; in fsl_pcib_attach()
337 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2); in fsl_pcib_attach()
338 if (cfgreg != 0x1057 && cfgreg != 0x1957) in fsl_pcib_attach()
341 capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1); in fsl_pcib_attach()
342 while (capptr != 0) { in fsl_pcib_attach()
343 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2); in fsl_pcib_attach()
344 switch (cfgreg & 0xff) { in fsl_pcib_attach()
352 capptr = (cfgreg >> 8) & 0xff; in fsl_pcib_attach()
368 if (fsl_pcib_decode_win(node, sc) != 0) in fsl_pcib_attach()
371 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2); in fsl_pcib_attach()
374 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2); in fsl_pcib_attach()
376 do_reset = 0; in fsl_pcib_attach()
380 brctl = fsl_pcib_read_config(sc->sc_dev, 0, 0, 0, in fsl_pcib_attach()
383 fsl_pcib_write_config(sc->sc_dev, 0, 0, 0, in fsl_pcib_attach()
387 fsl_pcib_write_config(sc->sc_dev, 0, 0, 0, in fsl_pcib_attach()
393 ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1); in fsl_pcib_attach()
398 return (0); in fsl_pcib_attach()
403 rid = 0; in fsl_pcib_attach()
408 if (error != 0) { in fsl_pcib_attach()
419 if (error != 0) { in fsl_pcib_attach()
423 if (error != 0) { in fsl_pcib_attach()
446 addr |= (bus & 0xff) << 16; in fsl_pcib_cfgread()
447 addr |= (slot & 0x1f) << 11; in fsl_pcib_cfgread()
448 addr |= (func & 0x7) << 8; in fsl_pcib_cfgread()
449 addr |= reg & 0xfc; in fsl_pcib_cfgread()
451 addr |= (reg & 0xf00) << 16; in fsl_pcib_cfgread()
470 data = ~0; in fsl_pcib_cfgread()
484 addr |= (bus & 0xff) << 16; in fsl_pcib_cfgwrite()
485 addr |= (slot & 0x1f) << 11; in fsl_pcib_cfgwrite()
486 addr |= (func & 0x7) << 8; in fsl_pcib_cfgwrite()
487 addr |= reg & 0xfc; in fsl_pcib_cfgwrite()
489 addr |= (reg & 0xf00) << 16; in fsl_pcib_cfgwrite()
511 #if 0
518 for (i = 0; i < 5; i++) {
519 printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i)));
520 printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i)));
521 printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i)));
522 printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i)));
526 printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i)));
527 printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i)));
528 printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i)));
529 printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i)));
534 for (i = 0; i < 0x48; i += 4) {
535 printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0,
546 return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX); in fsl_pcib_maxslots()
557 return (~0); in fsl_pcib_read_config()
580 KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__)); in fsl_pcib_inbound()
598 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0); in fsl_pcib_inbound()
611 attr = 0x80044000 | (ffsll(size) - 2); in fsl_pcib_outbound()
614 attr = 0x80088000 | (ffsll(size) - 2); in fsl_pcib_outbound()
617 attr = 0x0004401f; in fsl_pcib_outbound()
624 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0); in fsl_pcib_outbound()
638 sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2); in fsl_pcib_err_init()
640 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2); in fsl_pcib_err_init()
644 0xffffffff); in fsl_pcib_err_init()
646 0xffffffff); in fsl_pcib_err_init()
648 0xffffffff); in fsl_pcib_err_init()
650 dsr = fsl_pcib_cfgread(sc, 0, 0, 0, in fsl_pcib_err_init()
653 fsl_pcib_cfgwrite(sc, 0, 0, 0, in fsl_pcib_err_init()
655 0xffff, 2); in fsl_pcib_err_init()
658 err_en = 0x00bfff00; in fsl_pcib_err_init()
663 dcr = fsl_pcib_cfgread(sc, 0, 0, 0, in fsl_pcib_err_init()
667 fsl_pcib_cfgwrite(sc, 0, 0, 0, in fsl_pcib_err_init()
679 if (error != 0) in fsl_pcib_detach()
686 return (0); in fsl_pcib_detach()
697 fsl_pcib_outbound(sc, 0, -1, 0, 0, 0); in fsl_pcib_decode_win()
704 if (error != 0) { in fsl_pcib_decode_win()
709 for (i = 0; i < sc->pci_sc.sc_nrange; i++) { in fsl_pcib_decode_win()
742 if (error != 0) { in fsl_pcib_decode_win()
752 fsl_pcib_outbound(sc, 3, -1, 0, 0, 0); in fsl_pcib_decode_win()
753 fsl_pcib_outbound(sc, 4, -1, 0, 0, 0); in fsl_pcib_decode_win()
755 fsl_pcib_inbound(sc, 1, -1, 0, 0, 0); in fsl_pcib_decode_win()
756 fsl_pcib_inbound(sc, 2, -1, 0, 0, 0); in fsl_pcib_decode_win()
757 fsl_pcib_inbound(sc, 3, PIWAR_TRGT_LOCAL, 0, in fsl_pcib_decode_win()
758 ptoa(Maxmem), 0); in fsl_pcib_decode_win()
762 /* inbound window 8 makes it hit 0xD00 offset, the MSI window. */ in fsl_pcib_decode_win()
770 return (0); in fsl_pcib_decode_win()
782 err = vmem_xalloc(msi_vmem, count, powerof2(count), 0, 0, in fsl_pcib_alloc_msi()
788 for (i = 0; i < count; i++) in fsl_pcib_alloc_msi()
791 return (0); in fsl_pcib_alloc_msi()
800 vmem_xfree(msi_vmem, irqs[0], count); in fsl_pcib_release_msi()
801 return (0); in fsl_pcib_release_msi()
830 return (0); in fsl_pcib_map_msi()
843 #define FSL_MSI_TARGET 0x140
869 i = 0; in fsl_msi_intr_filter()
870 while (reg != 0) { in fsl_msi_intr_filter()
901 msi_vmem = vmem_create("MPIC MSI", 0, 0, 1, 0, M_BESTFIT | M_WAITOK); in fsl_msi_attach()
904 sc->sc_base = bus_get_resource_start(dev, SYS_RES_MEMORY, 0); in fsl_msi_attach()
907 if (sc->sc_map.target == 0) in fsl_msi_attach()
910 for (i = 0; i < FSL_NUM_IRQS; i++) { in fsl_msi_attach()
920 FSL_NUM_MSIS, 0, 0); in fsl_msi_attach()
927 return (0); in fsl_msi_attach()
956 EARLY_DRIVER_MODULE(fsl_msi, simplebus, fsl_msi_driver, 0, 0,