Lines Matching +full:cache +full:- +full:controller +full:- +full:0
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
41 * - mbar
42 * - isync
43 * - write
44 * - read
45 * - mbar
47 #define L2_CTL 0x0
48 #define L2CTL_L2E 0x80000000
49 #define L2CTL_L2I 0x40000000
55 {"fsl,8540-l2-cache-controller", 1},
56 {"fsl,8541-l2-cache-controller", 1},
57 {"fsl,8544-l2-cache-controller", 1},
58 {"fsl,8548-l2-cache-controller", 1},
59 {"fsl,8555-l2-cache-controller", 1},
60 {"fsl,8568-l2-cache-controller", 1},
61 {"fsl,b4420-l2-cache-controller", 1},
62 {"fsl,b4860-l2-cache-controller", 1},
63 {"fsl,bsc9131-l2-cache-controller", 1},
64 {"fsl,bsc9132-l2-cache-controller", 1},
65 {"fsl,c293-l2-cache-controller", 1},
66 {"fsl,mpc8536-l2-cache-controller", 1},
67 {"fsl,mpc8540-l2-cache-controller", 1},
68 {"fsl,mpc8541-l2-cache-controller", 1},
69 {"fsl,mpc8544-l2-cache-controller", 1},
70 {"fsl,mpc8548-l2-cache-controller", 1},
71 {"fsl,mpc8555-l2-cache-controller", 1},
72 {"fsl,mpc8560-l2-cache-controller", 1},
73 {"fsl,mpc8568-l2-cache-controller", 1},
74 {"fsl,mpc8569-l2-cache-controller", 1},
75 {"fsl,mpc8572-l2-cache-controller", 1},
76 {"fsl,p1010-l2-cache-controller", 1},
77 {"fsl,p1011-l2-cache-controller", 1},
78 {"fsl,p1012-l2-cache-controller", 1},
79 {"fsl,p1013-l2-cache-controller", 1},
80 {"fsl,p1014-l2-cache-controller", 1},
81 {"fsl,p1015-l2-cache-controller", 1},
82 {"fsl,p1016-l2-cache-controller", 1},
83 {"fsl,p1020-l2-cache-controller", 1},
84 {"fsl,p1021-l2-cache-controller", 1},
85 {"fsl,p1022-l2-cache-controller", 1},
86 {"fsl,p1023-l2-cache-controller", 1},
87 {"fsl,p1024-l2-cache-controller", 1},
88 {"fsl,p1025-l2-cache-controller", 1},
89 {"fsl,p2010-l2-cache-controller", 1},
90 {"fsl,p2020-l2-cache-controller", 1},
91 {"fsl,t2080-l2-cache-controller", 1},
92 {"fsl,t4240-l2-cache-controller", 1},
93 {0, 0}
100 if (ofw_bus_search_compatible(dev, compats)->ocd_str == NULL) in mpc85xx_cache_probe()
103 device_set_desc(dev, "MPC85xx L2 cache"); in mpc85xx_cache_probe()
104 return (0); in mpc85xx_cache_probe()
115 rid = 0; in mpc85xx_cache_attach()
116 sc->sc_mem = bus_alloc_resource_any(dev, in mpc85xx_cache_attach()
118 if (sc->sc_mem == NULL) in mpc85xx_cache_attach()
121 /* Enable cache and flash invalidate. */ in mpc85xx_cache_attach()
123 bus_write_4(sc->sc_mem, L2_CTL, L2CTL_L2E | L2CTL_L2I); in mpc85xx_cache_attach()
124 bus_read_4(sc->sc_mem, L2_CTL); in mpc85xx_cache_attach()
127 cache_line_size = 0; in mpc85xx_cache_attach()
128 cache_size = 0; in mpc85xx_cache_attach()
129 OF_getencprop(ofw_bus_get_node(dev), "cache-size", &cache_size, in mpc85xx_cache_attach()
131 OF_getencprop(ofw_bus_get_node(dev), "cache-line-size", in mpc85xx_cache_attach()
134 if (cache_line_size != 0 && cache_size != 0) in mpc85xx_cache_attach()
136 "L2 cache size: %dKB, cache line size: %d bytes\n", in mpc85xx_cache_attach()
139 return (0); in mpc85xx_cache_attach()
151 "cache",