Lines Matching +full:0 +full:x0a0

36 #define	LBC85XX_BR(n)	(0x0 + (8 * n))	/* Base register 0-7 */
37 #define	LBC85XX_OR(n)	(0x4 + (8 * n))	/* Options register 0-7 */
38 #define	LBC85XX_MAR	0x068		/* UPM address register */
39 #define	LBC85XX_MAMR	0x070		/* UPMA mode register */
40 #define	LBC85XX_MBMR	0x074		/* UPMB mode register */
41 #define	LBC85XX_MCMR	0x078		/* UPMC mode register */
42 #define	LBC85XX_MRTPR	0x084		/* Memory refresh timer prescaler */
43 #define	LBC85XX_MDR	0x088		/* UPM data register */
44 #define	LBC85XX_LSOR	0x090		/* Special operation initiation */
45 #define	LBC85XX_LURT	0x0a0		/* UPM refresh timer */
46 #define	LBC85XX_LSRT	0x0a4		/* SDRAM refresh timer */
47 #define	LBC85XX_LTESR	0x0b0		/* Transfer error status register */
48 #define	LBC85XX_LTEDR	0x0b4		/* Transfer error disable register */
49 #define	LBC85XX_LTEIR	0x0b8		/* Transfer error interrupt register */
50 #define	LBC85XX_LTEATR	0x0bc		/* Transfer error attributes register */
51 #define	LBC85XX_LTEAR	0x0c0		/* Transfer error address register */
52 #define	LBC85XX_LTECCR	0x0c4		/* Transfer error ECC register */
53 #define	LBC85XX_LBCR	0x0d0		/* Configuration register */
54 #define	LBC85XX_LCRR	0x0d4		/* Clock ratio register */
55 #define	LBC85XX_FMR	0x0e0		/* Flash mode register */
56 #define	LBC85XX_FIR	0x0e4		/* Flash instruction register */
57 #define	LBC85XX_FCR	0x0e8		/* Flash command register */
58 #define	LBC85XX_FBAR	0x0ec		/* Flash block address register */
59 #define	LBC85XX_FPAR	0x0f0		/* Flash page address register */
60 #define	LBC85XX_FBCR	0x0f4		/* Flash byte count register */
61 #define	LBC85XX_FECC0	0x100		/* Flash ECC block 0 register */
62 #define	LBC85XX_FECC1	0x104		/* Flash ECC block 0 register */
63 #define	LBC85XX_FECC2	0x108		/* Flash ECC block 0 register */
64 #define	LBC85XX_FECC3	0x10c		/* Flash ECC block 0 register */
67 #define	LBCRES_MSEL_GPCM	0
74 #define	LBCRES_DECC_DISABLED	0
79 #define	LBCRES_ATOM_DISABLED	0