Lines Matching +full:0 +full:x00000

34 #define	OPENPIC_SIZE			0x40000
37  * Per Processor Registers [private access] (0x00000 - 0x00fff)
41 #define	OPENPIC_IPI_DISPATCH(ipi)	(0x40 + (ipi) * 0x10)
44 #define	OPENPIC_TPR			0x80
45 #define  OPENPIC_TPR_MASK			0x0000000f
47 #define	OPENPIC_WHOAMI			0x90
50 #define	OPENPIC_IACK			0xa0
53 #define	OPENPIC_EOI			0xb0
56  * Global registers (0x01000-0x0ffff)
59 /* feature reporting reg 0 */
60 #define OPENPIC_FEATURE			0x1000
61 #define	 OPENPIC_FEATURE_VERSION_MASK		0x000000ff
62 #define	 OPENPIC_FEATURE_LAST_CPU_MASK		0x00001f00
64 #define	 OPENPIC_FEATURE_LAST_IRQ_MASK		0x07ff0000
67 /* global config reg 0 */
68 #define OPENPIC_CONFIG			0x1020
69 #define  OPENPIC_CONFIG_RESET			0x80000000
70 #define  OPENPIC_CONFIG_8259_PASSTHRU_DISABLE	0x20000000
73 #define OPENPIC_ICR			0x1030
75 #define  OPENPIC_ICR_SERIAL_RATIO_MASK		(0x7 << 28)
79 #define OPENPIC_VENDOR_ID		0x1080
82 #define OPENPIC_PROC_INIT		0x1090
85 #define OPENPIC_IPI_VECTOR(ipi)		(0x10a0 + (ipi) * 0x10)
88 #define OPENPIC_SPURIOUS_VECTOR		0x10e0
92 #define	OPENPIC_TFREQ			0x10f0
93 #define	OPENPIC_TCNT(t)			(0x1100 + (t) * 0x40)
94 #define	OPENPIC_TBASE(t)		(0x1110 + (t) * 0x40)
95 #define	OPENPIC_TVEC(t)			(0x1120 + (t) * 0x40)
96 #define	OPENPIC_TDST(t)			(0x1130 + (t) * 0x40)
99  * Interrupt Source Configuration Registers (0x10000 - 0x1ffff)
105 #define OPENPIC_SRC_VECTOR(irq)		(0x10000 + (irq) * 0x20)
107 #define  OPENPIC_SENSE_LEVEL			0x00400000
108 #define  OPENPIC_SENSE_EDGE			0x00000000
109 #define  OPENPIC_POLARITY_POSITIVE		0x00800000
110 #define  OPENPIC_POLARITY_NEGATIVE		0x00000000
111 #define  OPENPIC_IMASK				0x80000000
112 #define  OPENPIC_ACTIVITY			0x40000000
113 #define  OPENPIC_PRIORITY_MASK			0x000f0000
115 #define  OPENPIC_VECTOR_MASK			0x000000ff
119 #define OPENPIC_IDEST(irq)		(0x10010 + (irq) * 0x20)
123  * Per Processor Registers [global access] (0x20000 - 0x3ffff)
126 #define	OPENPIC_PCPU_BASE(cpu)		(0x20000 + (cpu) * 0x1000)