Lines Matching +full:bl +full:- +full:data +full:- +full:offset
1 /*-
2 * Copyright (C) 2006-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
29 /*-
53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
72 * SPRG0 - pcpu pointer
73 * SPRG1 - all interrupts except TLB miss, critical, machine check
74 * SPRG2 - critical
75 * SPRG3 - machine check
76 * SPRG4-6 - scratch
80 /* Get the per-CPU data structure */
84 #define RES_LOCK 0 /* offset to the 'lock' word */
86 #define RES_RECURSE 8 /* offset to the 'recurse' word */
88 #define RES_RECURSE 4 /* offset to the 'recurse' word */
94 * sprg_sp - SPRG{1-3} reg used to temporarily store the SP
95 * savearea - temp save area (pc_{tempsave, disisave, critsave, mchksave})
96 * isrr0-1 - save restore registers with CPU state at interrupt time (may be
97 * SRR0-1, CSRR0-1, MCSRR0-1
100 * - R30-31
101 * - DEAR, ESR
102 * - xSRR0-1
104 * 2. saves CR -> R30
109 * - R31 can be used as scratch register until a new frame is laid on
112 * - potential TLB miss: NO. Saveareas are always acessible via TLB1
118 GET_CPUINFO(%r1); /* Per-cpu structure */ \
132 /* switch to per-thread kstack if intr taken in user mode */ \
135 GET_CPUINFO(%r1); /* Per-cpu structure */ \
136 LOAD %r1, PC_CURPCB(%r1); /* Per-thread kernel stack */ \
141 GET_CPUINFO(%r1); /* Per-cpu structure */ \
159 /* switch to per-thread kstack if intr taken in user mode */ \
162 GET_CPUINFO(%r1); /* Per-cpu structure */ \
163 LOAD %r1, PC_CURPCB(%r1); /* Per-thread kernel stack */ \
168 * SPRG{1-3} SP at the time interrupt occurred
169 * savearea r30-r31, DEAR, ESR, xSRR0-1
174 * sprg_sp - SPRG reg containing SP at the time interrupt occurred
175 * savearea - temp save
176 * exc - exception number (EXC_xxx)
180 * - R0, R1 (SP at the time of interrupt), R2, LR, CR
181 * - R3-31 (R30-31 first restored from savearea)
182 * - XER, CTR, DEAR, ESR (from savearea), xSRR0-1
185 * - potential TLB miss: YES, since we make dereferences to kstack, which
260 STU %r31, -(FRAMELEN+REDZONE)(%r1); \
270 /* save R3-31 */ \
287 /* save xSSR0-1 */ \
296 * isrr0-1 - save restore registers to restore CPU state to (may be
297 * SRR0-1, CSRR0-1, MCSRR0-1
300 * - potential TLB miss: YES. The deref'd kstack may be not covered
316 /* restore xSRR0-1 */ \
321 /* restore R2-31, SP */ \
331 * saves LR, CR, SRR0-1, R20-31 in the TLBSAVE area
334 * - potential TLB miss: NO. It is crucial that we do not generate a TLB
336 * - TLBSAVE is always translated
380 GET_CPUINFO(%r1); /* Per-cpu structure */ \
388 /* save R20-31 */ \
397 /* save SRR0-1 */ \
406 * restores LR, CR, SRR0-1, R20-31 from the TLBSAVE area
412 GET_CPUINFO(%r1); /* Per-cpu structure */ \
426 /* restore SRR0-1 */ \
431 /* restore R20-31 */ \
447 bne- 1b; \
451 bne- 1b; \
492 * to live in pre-defined vectors location. Note they need to be TLB-mapped at
494 * them to be part of kernel text which is always TLB-accessible.
505 * Catch-all handler to handle uninstalled IVORs
520 bl CNAME(powerpc_interrupt)
534 bl CNAME(powerpc_interrupt)
541 * Data storage interrupt
647 bl spe_handle_fpdata
655 bl spe_handle_fpround
673 * Data TLB miss interrupt
675 * There can be nested TLB misses - while handling a TLB miss we reference
676 * data structures that may be not covered by translations. We support up to
677 * TLB_NESTED_MAX-1 nested misses.
680 * r31 - dear
681 * r30 - unused
682 * r29 - saved mas0
683 * r28 - saved mas1
684 * r27 - saved mas2
685 * r26 - pmap address
686 * r25 - pte address
688 * r20:r23 - scratch registers
697 * Save MAS0-MAS2 registers. There might be another tlb miss during
725 bl 1f
727 .llong kernel_pmap_store-.
729 .long kernel_pmap_store-.
741 bl pte_lookup /* returns PTE address in R25 */
747 bl tlb_fill_entry
789 * input: r26 - pmap
790 * input: r31 - dear
791 * output: r25 - pte address
801 rldicl %r21, %r31, (64 - PG_ROOT_L), (64 - PG_ROOT_NUM) /* pp2d offset */
804 ldx %r25, %r25, %r21 /* get pdir address, i.e. pmap->pm_pp2d[pp2d_idx] * */
809 rldicl %r21, %r31, (64 - PDIR_L1_L), (64 - PDIR_L1_NUM) /* pp2d offset */
811 ldx %r25, %r25, %r21 /* get pdir address, i.e. pmap->pm_pp2d[pp2d_idx] * */
816 rldicl %r21, %r31, (64 - PDIR_L), (64 - PDIR_NUM) /* pdir offset */
818 ldx %r25, %r25, %r21 /* get ptbl address, i.e. pmap->pm_pp2d[pp2d_idx][pdir_idx] */
823 rldicl %r21, %r31, (64 - PTBL_L), (64 - PTBL_NUM) /* ptbl offset */
827 srwi %r21, %r31, PDIR_SHIFT /* pdir offset */
832 * Get ptbl address, i.e. pmap->pm_pdir[pdir_idx]
833 * This load may cause a Data TLB miss for non-kernel pmap!
835 lwzx %r25, %r25, %r21 /* offset within pm_pdir[] table */
843 /* ptbl offset, multiply by ptbl entry size */
844 srwi %r21, %r21, (PTBL_SHIFT - PTBL_ENTRY_SHIFT)
849 * Get pte->flags
850 * This load may cause a Data TLB miss for non-kernel pmap!
862 * Load MAS1-MAS3 registers with data, write TLB entry
865 * r29 - mas0
866 * r28 - mas1
867 * r27 - mas2
868 * r25 - pte
872 * scratch regs: r21-r23
883 lwarx %r21, %r23, %r25 /* get pte->flags */
891 bne- 1b
897 LOAD %r23, PTE_RPN(%r25) /* get pte->rpn */
927 * Same notes as for the Data TLB miss
936 * Save MAS0-MAS2 registers. There might be another tlb miss during pte
960 bl int_debug_int
967 bl int_debug_int
973 /* Common code between e500v1/v2 and e500mc-based cores. */
978 bl 0f
979 ADDR(interrupt_vector_base-.)
980 ADDR(interrupt_vector_top-.)
991 /* Disable single-stepping for the interrupt handlers. */
1011 bl CNAME(powerpc_interrupt)
1019 /* Test AST pending - makes sense for user process only */
1030 /* re-enable interrupts before calling ast() */
1034 bl CNAME(ast)
1086 bl CNAME(db_trap_glue)
1107 bne- 1b
1129 .data