Lines Matching +full:0 +full:x2e0
70 #define EVSTDW(n) __asm ("evstdw %1,0(%0)" \ in save_vec_int()
72 EVSTDW(0); EVSTDW(1); EVSTDW(2); EVSTDW(3); in save_vec_int()
82 __asm ( "evxor 0,0,0\n" in save_vec_int()
83 "evmwumiaa 0,0,0\n" in save_vec_int()
84 "evstdd 0,0(%0)" :: "b"(&pcb->pcb_vec.spare[0])); in save_vec_int()
115 * the thread, initialise the vector registers and VSCR to 0, and in enable_vec()
120 memset(&pcb->pcb_vec, 0, sizeof pcb->pcb_vec); in enable_vec()
134 __asm __volatile("isync;evldd 0, 0(%0); evmra 0,0\n" in enable_vec()
135 :: "b"(&pcb->pcb_vec.spare[0])); in enable_vec()
141 #define EVLDW(n) __asm __volatile("evldw 0, 0(%0); evmergehilo "#n",0,"#n \ in enable_vec()
150 EVLDW(29); EVLDW(30); EVLDW(31); EVLDW(0); in enable_vec()
191 for (i = 0; i < 32; i++) { in save_vec_nodrop()
193 td->td_frame ? td->td_frame->fixreg[i] : 0; in save_vec_nodrop()
197 #define SPE_INST_MASK 0x31f
198 #define EADD 0x200
199 #define ESUB 0x201
200 #define EABS 0x204
201 #define ENABS 0x205
202 #define ENEG 0x206
203 #define EMUL 0x208
204 #define EDIV 0x209
205 #define ECMPGT 0x20c
206 #define ECMPLT 0x20d
207 #define ECMPEQ 0x20e
208 #define ECFUI 0x210
209 #define ECFSI 0x211
210 #define ECTUI 0x214
211 #define ECTSI 0x215
212 #define ECTUF 0x216
213 #define ECTSF 0x217
214 #define ECTUIZ 0x218
215 #define ECTSIZ 0x21a
217 #define SPE 0x4
218 #define SPFP 0x6
219 #define DPFP 0x7
224 #define EVFSADD 0x280
225 #define EVFSSUB 0x281
226 #define EVFSABS 0x284
227 #define EVFSNABS 0x285
228 #define EVFSNEG 0x286
229 #define EVFSMUL 0x288
230 #define EVFSDIV 0x289
231 #define EVFSCMPGT 0x28c
232 #define EVFSCMPLT 0x28d
233 #define EVFSCMPEQ 0x28e
234 #define EVFSCFUI 0x290
235 #define EVFSCFSI 0x291
236 #define EVFSCTUI 0x294
237 #define EVFSCTSI 0x295
238 #define EVFSCTUF 0x296
239 #define EVFSCTSF 0x297
240 #define EVFSCTUIZ 0x298
241 #define EVFSCTSIZ 0x29a
243 #define EFSADD 0x2c0
244 #define EFSSUB 0x2c1
245 #define EFSABS 0x2c4
246 #define EFSNABS 0x2c5
247 #define EFSNEG 0x2c6
248 #define EFSMUL 0x2c8
249 #define EFSDIV 0x2c9
250 #define EFSCMPGT 0x2cc
251 #define EFSCMPLT 0x2cd
252 #define EFSCMPEQ 0x2ce
253 #define EFSCFD 0x2cf
254 #define EFSCFUI 0x2d0
255 #define EFSCFSI 0x2d1
256 #define EFSCTUI 0x2d4
257 #define EFSCTSI 0x2d5
258 #define EFSCTUF 0x2d6
259 #define EFSCTSF 0x2d7
260 #define EFSCTUIZ 0x2d8
261 #define EFSCTSIZ 0x2da
263 #define EFDADD 0x2e0
264 #define EFDSUB 0x2e1
265 #define EFDABS 0x2e4
266 #define EFDNABS 0x2e5
267 #define EFDNEG 0x2e6
268 #define EFDMUL 0x2e8
269 #define EFDDIV 0x2e9
270 #define EFDCMPGT 0x2ec
271 #define EFDCMPLT 0x2ed
272 #define EFDCMPEQ 0x2ee
273 #define EFDCFS 0x2ef
274 #define EFDCFUI 0x2f0
275 #define EFDCFSI 0x2f1
276 #define EFDCTUI 0x2f4
277 #define EFDCTSI 0x2f5
278 #define EFDCTUF 0x2f6
279 #define EFDCTSF 0x2f7
280 #define EFDCTUIZ 0x2f8
281 #define EFDCTSIZ 0x2fa
294 spefscr = 0; in fpscr_to_spefscr()
310 /* Sign is 0 for unsigned, 1 for signed. */
316 res[0] = fpu_ftox(fpemu, fpn, res); in spe_to_int()
317 if (res[0] != UINT_MAX && res[0] != 0) in spe_to_int()
319 else if (sign == 0 && res[0] != 0) in spe_to_int()
324 return (0); in spe_to_int()
329 * For compare instructions, returns 1 if success, 0 if not. For all others,
346 spe_to_int(fpemu, &fpemu->fe_f2, iresult, 0); in spe_emu_instr()
367 fpu_compare(fpemu, 0); in spe_emu_instr()
370 return (0); in spe_emu_instr()
372 fpu_compare(fpemu, 0); in spe_emu_instr()
375 return (0); in spe_emu_instr()
377 fpu_compare(fpemu, 0); in spe_emu_instr()
380 return (0); in spe_emu_instr()
395 fp->fp_sticky = 0; in spe_explode()
406 if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) { in spe_explode()
414 fp->fp_mant[0] |= FP_QUIETBIT; in spe_explode()
420 return (0); in spe_explode()
430 #define EVSTDW(n) case n: __asm __volatile ("evstdw %1,0(%0)" \ in spe_save_reg_high()
433 EVSTDW(0); EVSTDW(1); EVSTDW(2); EVSTDW(3); in spe_save_reg_high()
444 return (vec[0]); in spe_save_reg_high()
453 #define EVLDW(n) case n: __asm __volatile("evmergelo "#n",%0,"#n \ in spe_load_reg_high()
463 EVLDW(29); EVLDW(30); EVLDW(31); EVLDW(0); in spe_load_reg_high()
477 uint32_t spefscr = 0; in spe_handle_fpdata()
485 if (err != 0) in spe_handle_fpdata()
499 rd = (instr >> 21) & 0x1f; in spe_handle_fpdata()
500 ra = (instr >> 16) & 0x1f; in spe_handle_fpdata()
501 rb = (instr >> 11) & 0x1f; in spe_handle_fpdata()
502 src = (instr >> 5) & 0x7; in spe_handle_fpdata()
503 cr_shift = 28 - (rd & 0x1f); in spe_handle_fpdata()
505 instr_sec_op = (instr & 0x7ff); in spe_handle_fpdata()
507 memset(&fpemu, 0, sizeof(fpemu)); in spe_handle_fpdata()
532 spe_save_reg_high(ra), 0); in spe_handle_fpdata()
534 spe_save_reg_high(rb), 0); in spe_handle_fpdata()
538 if (high < 0) in spe_handle_fpdata()
543 memset(&fpemu, 0, sizeof(fpemu)); in spe_handle_fpdata()
547 frame->fixreg[ra], 0); in spe_handle_fpdata()
549 frame->fixreg[rb], 0); in spe_handle_fpdata()
585 frame->fixreg[ra], 0); in spe_handle_fpdata()
587 frame->fixreg[rb], 0); in spe_handle_fpdata()
611 frame->fixreg[rb], 0); in spe_handle_fpdata()
641 frame->cr &= ~(0xf << cr_shift); in spe_handle_fpdata()