53 static register_t bsp_state[8] __aligned(8);  variable
76 		mtspr(SPR_HID4, bsp_state[2]); powerpc_sync(); isync();  in cpudep_ap_early_bootstrap()
77 		mtspr(SPR_HID5, bsp_state[3]); powerpc_sync(); isync();  in cpudep_ap_early_bootstrap()
81 		    : "=r"(reg) : "K"(SPR_HID4), "b"(bsp_state));  in cpudep_ap_early_bootstrap()
84 		    : "=r"(reg) : "K"(SPR_HID5), "b"(bsp_state));  in cpudep_ap_early_bootstrap()
254 		bsp_state[0] = mfspr(SPR_HID0);  in cpudep_save_config()
255 		bsp_state[1] = mfspr(SPR_HID1);  in cpudep_save_config()
256 		bsp_state[2] = mfspr(SPR_HID4);  in cpudep_save_config()
257 		bsp_state[3] = mfspr(SPR_HID5);  in cpudep_save_config()
260 		    : "=r" (bsp_state[0]),"=r" (bsp_state[1]) : "K" (SPR_HID0));  in cpudep_save_config()
262 		    : "=r" (bsp_state[2]),"=r" (bsp_state[3]) : "K" (SPR_HID1));  in cpudep_save_config()
264 		    : "=r" (bsp_state[4]),"=r" (bsp_state[5]) : "K" (SPR_HID4));  in cpudep_save_config()
266 		    : "=r" (bsp_state[6]),"=r" (bsp_state[7]) : "K" (SPR_HID5));  in cpudep_save_config()
275 			bsp_state[0] = mfspr(SPR_HID0);  in cpudep_save_config()
276 			bsp_state[1] = mfspr(SPR_HID1);  in cpudep_save_config()
277 			bsp_state[2] = mfspr(SPR_HID4);  in cpudep_save_config()
278 			bsp_state[3] = mfspr(SPR_HID6);  in cpudep_save_config()
280 			bsp_state[4] = mfspr(SPR_CELL_TSCR);  in cpudep_save_config()
284 		bsp_state[5] = mfspr(SPR_CELL_TSRL);  in cpudep_save_config()
291 		bsp_state[3] = mfspr(SPR_L3CR);  in cpudep_save_config()
298 		bsp_state[2] = mfspr(SPR_L2CR);  in cpudep_save_config()
299 		bsp_state[1] = mfspr(SPR_HID1);  in cpudep_save_config()
300 		bsp_state[0] = mfspr(SPR_HID0);  in cpudep_save_config()
335 		    :: "r"(bsp_state[0]), "K"(SPR_HID0));  in cpudep_ap_setup()
338 		    :: "r"(bsp_state[1]), "K"(SPR_HID1));  in cpudep_ap_setup()
347 		    : "=r"(reg) : "K"(SPR_HID0), "b"(bsp_state));  in cpudep_ap_setup()
350 		    : "=r"(reg) : "K"(SPR_HID1), "b"(bsp_state));  in cpudep_ap_setup()
358 			mtspr(SPR_HID0, bsp_state[0]);  in cpudep_ap_setup()
359 			mtspr(SPR_HID1, bsp_state[1]);  in cpudep_ap_setup()
360 			mtspr(SPR_HID4, bsp_state[2]);  in cpudep_ap_setup()
361 			mtspr(SPR_HID6, bsp_state[3]);  in cpudep_ap_setup()
363 			mtspr(SPR_CELL_TSCR, bsp_state[4]);  in cpudep_ap_setup()
367 		mtspr(SPR_CELL_TSRL, bsp_state[5]);  in cpudep_ap_setup()
383 		mtspr(SPR_HID0, bsp_state[0]); isync();  in cpudep_ap_setup()
384 		mtspr(SPR_HID1, bsp_state[1]); isync();  in cpudep_ap_setup()
392 			mpc745x_l3_enable(bsp_state[3]);  in cpudep_ap_setup()
397 		mpc74xx_l2_enable(bsp_state[2]);  in cpudep_ap_setup()