Lines Matching +full:self +full:- +full:advertising

1 /*-
14  * 3. All advertising materials mentioning features or use of this software
31 /*-
140 /* Bits for running on 64-bit systems in 32-bit mode. */
181 	 * may internally use non-1:1 mappings.
210 		 * makes them pretend they have a 32-byte cacheline. Turn this
228 			/* XXX: get from ibm,slb-size in device tree */
280 	 * process uses a conditionally-enabled facility.
290 	 * Bits 1-4, 10-15 (ppc32), 33-36, 42-47 (ppc64)
296 	 * size and whether or not we need the 64-bit bridge code.
302 	 * translation is re-enabled.
312 	 * anyway, we know it exists, and we know it is cache-aligned.
335 	 * executing an instruction that is only legal on 64-bit PPC (mtmsrd),
361 		/* Patch the two instances of rfi -> rfid */
372 	trapsize = (size_t)&trapcodeend - (size_t)&trapcode;
384 		 * Copy a code snippet to restore 32-bit bridge mode
385 		 * to the top of every non-generic trap handler
416 	trapsize = (size_t)&hypertrapcodeend - (size_t)&hypertrapcode;
424 	bcopy(&rstcode, (void *)(EXC_RST + trap_offset), (size_t)&rstcodeend -
428 	bcopy(&dblow, (void *)(EXC_MCHK + trap_offset), (size_t)&dbend -
430 	bcopy(&dblow, (void *)(EXC_PGM + trap_offset), (size_t)&dbend -
432 	bcopy(&dblow, (void *)(EXC_TRC + trap_offset), (size_t)&dbend -
434 	bcopy(&dblow, (void *)(EXC_BPT + trap_offset), (size_t)&dbend -
437 	bcopy(&alitrap,  (void *)(EXC_ALI + trap_offset),  (size_t)&aliend -
439 	bcopy(&dsitrap,  (void *)(EXC_DSI + trap_offset),  (size_t)&dsiend -
442 	/* Set address of generictrap for self-reloc calculations */
456 	/* G2-specific TLB miss helper handlers */
461 	__syncicache(EXC_RSVD, EXC_LAST - EXC_RSVD);
501 	tf = td->td_frame;
502 	tf->srr1 |= PSL_SE;
512 	tf = td->td_frame;
513 	tf->srr1 &= ~PSL_SE;
522 	kdb_frame->srr1 &= ~PSL_SE;
529 	kdb_frame->srr1 |= PSL_SE;
540 memcpy(pcpu->pc_aim.slb, PCPU_GET(aim.slb), sizeof(pcpu->pc_aim.slb));
550 	 * This block is 64-bit CPU specific currently.  Punt running in 32-bit
551 	 * mode on 64-bit CPUs.
554 	if ((frame->srr1 & SRR1_MCHK_DATA) != 0) {
555 		printf("Machine check, DSISR: %016lx\n", frame->cpu.aim.dsisr);
556 		/* SLB multi-hit is recoverable. */
557 		if ((frame->cpu.aim.dsisr & DSISR_MC_SLB_MULTIHIT) != 0)
559 		if ((frame->cpu.aim.dsisr &
566 		if ((frame->srr1 & SRR1_MCHK_IFETCH_M) == SRR1_MCHK_IFETCH_SLBMH)
578 	return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK);
608  * rely on existing mappings/real mode, unmap is a no-op.
630 		virtual_avail += round_page(size + pa - trunc_page(pa));
643 /* From p3-53 of the MPC7450 RISC Microprocessor Family Reference Manual */
794 	/* XXX: The mttb() means this *only* works on single-CPU systems. */
797 	PCPU_SET(curpcb, curthread->td_pcb);