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1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2013 George V. Neville-Neil
33 * The following set of constants are from Document SFF-8472
43 * 0-95 Serial ID Defined by SFP MSA
44 * 96-127 Vendor Specific Data
45 * 128-255 Reserved
48 * 0-55 Alarm and Warning Thresholds
49 * 56-95 Cal Constants
50 * 96-119 Real Time Diagnostic Interface
51 * 120-127 Vendor Specific
52 * 128-247 User Writable EEPROM
53 * 248-255 Vendor Specific
65 /* Table 3.1 Two-wire interface ID: Data Fields */
98 * 20-35] */
125 SFF_8472_BR_MAX = 66, /* BR max Upper bit rate margin,
128 SFF_8472_BR_MIN = 67, /* Lower bit rate margin, units of
131 SFF_8472_SN_START = 68, /* Vendor SN [Address A0h, Bytes 68-83] */
147 SFF_8472_COMPLIANCE = 94, /* SFF-8472 Compliance Indicates
148 * which revision of SFF-8472 the
167 * See SFF-8472 doc. */
206 * - Rx optical power. Bit 7 of
207 * byte 56 is MSB. Bit 0 of byte
213 * - Rx optical power. Bit 7 of
214 * byte 60 is MSB. Bit 0 of byte 63
220 * Rx optical power. Bit 7 of byte
221 * 64 is MSB, bit 0 of byte 67 is
227 * Rx optical power. Bit 7 of byte
228 * 68 is MSB, bit 0 of byte 71 is
234 * Rx optical power. Bit 7 of byte
235 * 72 is MSB, bit 0 of byte 75 is
241 * laser bias current. Bit 7 of
242 * byte 76 is MSB, bit 0 of byte 77
249 * current. Bit 7 of byte 78 is
250 * MSB, bit 0 of byte 79 is
257 * power. Bit 7 of byte 80 is MSB,
258 * bit 0 of byte 81 is LSB.
265 * coupled output power. Bit 7 of
266 * byte 82 is MSB, bit 0 of byte 83
272 * internal module temperature. Bit
273 * 7 of byte 84 is MSB, bit 0 of
280 * temperature. Bit 7 of byte 86 is
281 * MSB, bit 0 of byte 87 is LSB.
288 * voltage. Bit 7 of byte 88 is
289 * MSB, bit 0 of byte 89 is
296 * voltage. Bit 7 of byte 90 is
297 * MSB. Bit 0 of byte 91 is
325 * Select Read/write bit that allows software disable of
327 * enable/disable timing requirements. This bit is “OR”d with the hard
330 * implemented, the transceiver ignores the value of this bit. Default
336 * RS(1) State Digital state of SFP input pin AS(1) per SFF-8079 or
337 * RS(1) per SFF-8431. Updated within 100ms of change on pin. See A2h
338 * Byte 118, Bit 3 for Soft RS(1) Select control information.
345 * This pin is also known as AS(0) in SFF-8079 and RS(0) in SFF-8431.
350 * Read/write bit that allows software rate select control. Writing
351 * ‘1’ selects full bandwidth operation. This bit is “OR’d with the
355 * of this bit. Note: Specific transceiver behaviors of this bit are
357 * byte 118, bit 3 for Soft RS(1) Select.
374 * Indicates transceiver has achieved power up and data is ready. Bit
376 * device sets the bit low.
382 * Identifier constants has taken from SFF-8024 rev 4.6 table 4.1
394 SFF_8024_ID_XFPE = 0x8, /* XFP-E */
397 SFF_8024_ID_DWDM_SFP = 0xB, /* DWDM-SFP */
410 SFF_8024_ID_QSFP_DD = 0x18, /* QSFP-DD 8X Pluggable Transceiver */
412 SFF_8024_ID_SFP_DD = 0x1A, /* SFP-DD 2X Pluggable Transceiver */
431 "XFP-E",
434 "DWDM-SFP/SFP+",
447 "QSFP-DD",
449 "SFP-DD",
511 * Represented as a 16 bit unsigned integer with the voltage defined
512 * as the full 16 bit value (0 – 65535) with LSB equal to 100 uVolt,
518 * Represented as a 16 bit unsigned integer with the current defined
519 * as the full 16 bit value (0 – 65535) with LSB equal to 2 uA,
526 * Represented as a 16 bit unsigned integer with the power defined as
527 * the full 16 bit value (0 – 65535) with LSB equal to 0.1 uW,
528 * yielding a total range of 0 to 6.5535 mW (~ -40 to +8.2 dBm).