1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
58 	uint64_t base;  member
84     "Enable support for PCI-e memory mapped config access");
101  * numbers in the range 128-254 to indicate something strange and
192 		return (-1);  in pci_docfgregread()
247 /* enable configuration space accesses and return data port address */
259 	    && (reg & (bytes - 1)) == 0) {  in pci_cfgenable()
287 		 * Writing a 0 to the address port can apparently  in pci_cfgdisable()
301 	int data = -1;  in pcireg_cfgread()
302 	int port;  in pcireg_cfgread()  local
305 	port = pci_cfgenable(bus, slot, func, reg, bytes);  in pcireg_cfgread()
306 	if (port != 0) {  in pcireg_cfgread()
309 			data = inb(port);  in pcireg_cfgread()
312 			data = inw(port);  in pcireg_cfgread()
315 			data = inl(port);  in pcireg_cfgread()
327 	int port;  in pcireg_cfgwrite()  local
330 	port = pci_cfgenable(bus, slot, func, reg, bytes);  in pcireg_cfgwrite()
331 	if (port != 0) {  in pcireg_cfgwrite()
334 			outb(port, data);  in pcireg_cfgwrite()
337 			outw(port, data);  in pcireg_cfgwrite()
340 			outl(port, data);  in pcireg_cfgwrite()
355 	int port;  in pci_cfgcheck()  local
364 		port = pci_cfgenable(0, device, 0, 0, 4);  in pci_cfgcheck()
365 		id = inl(port);  in pci_cfgcheck()
369 		port = pci_cfgenable(0, device, 0, 8, 4);  in pci_cfgcheck()
370 		class = inl(port) >> 8;  in pci_cfgcheck()
376 		port = pci_cfgenable(0, device, 0, 14, 1);  in pci_cfgcheck()
377 		header = inb(port);  in pci_cfgcheck()
390 		printf("-- nothing found\n");  in pci_cfgcheck()
406 		printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08x\n",  in pcireg_cfgopen()
444 		printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",  in pcireg_cfgopen()
502 		pcielist = &pcie_list[pc->pc_cpuid];  in pcie_init_cache()
509 			elem->vapage = va + (i * PAGE_SIZE);  in pcie_init_cache()
510 			elem->papage = 0;  in pcie_init_cache()
525 	 * inaccessible using memory-mapped PCI config access.  Walk  in pcie_init_badslots()
543 pcie_cfgregopen(uint64_t base, uint16_t domain, uint8_t minbus, uint8_t maxbus)  in pcie_cfgregopen()  argument
550 	if (!pae_mode && base >= 0x100000000) {  in pcie_cfgregopen()
553 	    "PCI: MCFG domain %u bus %u-%u base 0x%jx too high\n",  in pcie_cfgregopen()
554 			domain, minbus, maxbus, (uintmax_t)base);  in pcie_cfgregopen()
559 		printf("PCI: MCFG domain %u bus %u-%u base @ 0x%jx\n",  in pcie_cfgregopen()
560 		    domain, minbus, maxbus, (uintmax_t)base);  in pcie_cfgregopen()
564 			pcie_cache_initted = -1;  in pcie_cfgregopen()
569 	if (pcie_cache_initted == -1)  in pcie_cfgregopen()
577 	region->base = base + (minbus << 20);  in pcie_cfgregopen()
578 	region->domain = domain;  in pcie_cfgregopen()
579 	region->minbus = minbus;  in pcie_cfgregopen()
580 	region->maxbus = maxbus;  in pcie_cfgregopen()
592 #define PCIE_PADDR(base, reg, bus, slot, func)	\  argument
593 	((base)				+	\
607 	MPASS(bus >= region->minbus && bus <= region->maxbus);  in pciereg_findaddr()
609 	pa = PCIE_PADDR(region->base, reg, bus - region->minbus, slot, func);  in pciereg_findaddr()
620 		if (elem->papage == papage)  in pciereg_findaddr()
626 		if (elem->papage != 0) {  in pciereg_findaddr()
627 			pmap_kremove(elem->vapage);  in pciereg_findaddr()
628 			invlpg(elem->vapage);  in pciereg_findaddr()
630 		pmap_kenter(elem->vapage, papage);  in pciereg_findaddr()
631 		elem->papage = papage;  in pciereg_findaddr()
638 	return (elem->vapage | (pa & PAGE_MASK));  in pciereg_findaddr()
654 	int data = -1;  in pciereg_cfgread()
657 		return (-1);  in pciereg_cfgread()