Lines Matching +full:0 +full:xa8000
109 #size-cells = <0>;
111 cpu0: PowerPC,e5500@0 {
113 reg = <0>;
135 dcsr-epu@0 {
137 interrupts = <52 2 0 0
138 84 2 0 0
139 85 2 0 0>;
141 reg = <0x0 0x1000>;
145 reg = <0x1000 0x1000 0x1000000 0x8000>;
149 reg = <0x2000 0x1000>;
153 reg = <0x8000 0x1000 0xB0000 0x1000>;
157 reg = <0x9000 0x1000>;
161 reg = <0x11000 0x1000>;
166 reg = <0x12000 0x1000>;
171 reg = <0x13000 0x1000>;
175 reg = <0x18000 0x1000>;
179 reg = <0x22000 0x1000>;
184 reg = <0x40000 0x1000>;
189 reg = <0x41000 0x1000>;
194 #address-cells = <0x1>;
195 #size-cells = <0x1>;
197 ranges = <0x0 0xf 0xfde00000 0x200000>;
198 bman-portal@0 {
199 cell-index = <0x0>;
201 reg = <0x0 0x4000 0x100000 0x1000>;
202 interrupts = <105 2 0 0>;
205 cell-index = <0x1>;
207 reg = <0x4000 0x4000 0x101000 0x1000>;
208 interrupts = <107 2 0 0>;
213 reg = <0x8000 0x4000 0x102000 0x1000>;
214 interrupts = <109 2 0 0>;
217 cell-index = <0x3>;
219 reg = <0xc000 0x4000 0x103000 0x1000>;
220 interrupts = <111 2 0 0>;
223 cell-index = <0x4>;
225 reg = <0x10000 0x4000 0x104000 0x1000>;
226 interrupts = <113 2 0 0>;
229 cell-index = <0x5>;
231 reg = <0x14000 0x4000 0x105000 0x1000>;
232 interrupts = <115 2 0 0>;
235 cell-index = <0x6>;
237 reg = <0x18000 0x4000 0x106000 0x1000>;
238 interrupts = <117 2 0 0>;
241 cell-index = <0x7>;
243 reg = <0x1c000 0x4000 0x107000 0x1000>;
244 interrupts = <119 2 0 0>;
247 cell-index = <0x8>;
249 reg = <0x20000 0x4000 0x108000 0x1000>;
250 interrupts = <121 2 0 0>;
253 cell-index = <0x9>;
255 reg = <0x24000 0x4000 0x109000 0x1000>;
256 interrupts = <123 2 0 0>;
259 buffer-pool@0 {
261 fsl,bpid = <0>;
262 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
267 #address-cells = <0x1>;
268 #size-cells = <0x1>;
270 ranges = <0x0 0xf 0xfdc00000 0x200000>;
271 qportal0: qman-portal@0 {
272 cell-index = <0x0>;
274 reg = <0x0 0x4000 0x100000 0x1000>;
275 interrupts = <104 0x2 0 0>;
276 fsl,qman-channel-id = <0x0>;
280 cell-index = <0x1>;
282 reg = <0x4000 0x4000 0x101000 0x1000>;
283 interrupts = <106 0x2 0 0>;
284 fsl,qman-channel-id = <0x1>;
288 cell-index = <0x2>;
290 reg = <0x8000 0x4000 0x102000 0x1000>;
291 interrupts = <108 0x2 0 0>;
292 fsl,qman-channel-id = <0x2>;
296 cell-index = <0x3>;
298 reg = <0xc000 0x4000 0x103000 0x1000>;
299 interrupts = <110 0x2 0 0>;
300 fsl,qman-channel-id = <0x3>;
304 cell-index = <0x4>;
306 reg = <0x10000 0x4000 0x104000 0x1000>;
307 interrupts = <112 0x2 0 0>;
308 fsl,qman-channel-id = <0x4>;
312 cell-index = <0x5>;
314 reg = <0x14000 0x4000 0x105000 0x1000>;
315 interrupts = <114 0x2 0 0>;
316 fsl,qman-channel-id = <0x5>;
320 cell-index = <0x6>;
322 reg = <0x18000 0x4000 0x106000 0x1000>;
323 interrupts = <116 0x2 0 0>;
324 fsl,qman-channel-id = <0x6>;
328 cell-index = <0x7>;
330 reg = <0x1c000 0x4000 0x107000 0x1000>;
331 interrupts = <118 0x2 0 0>;
332 fsl,qman-channel-id = <0x7>;
336 cell-index = <0x8>;
338 reg = <0x20000 0x4000 0x108000 0x1000>;
339 interrupts = <120 0x2 0 0>;
340 fsl,qman-channel-id = <0x8>;
344 cell-index = <0x9>;
346 reg = <0x24000 0x4000 0x109000 0x1000>;
347 interrupts = <122 0x2 0 0>;
348 fsl,qman-channel-id = <0x9>;
354 fsl,qman-channel-id = <0x21>;
360 fsl,qman-channel-id = <0x22>;
366 fsl,qman-channel-id = <0x23>;
372 fsl,qman-channel-id = <0x24>;
378 fsl,qman-channel-id = <0x25>;
384 fsl,qman-channel-id = <0x26>;
390 fsl,qman-channel-id = <0x27>;
396 fsl,qman-channel-id = <0x28>;
402 fsl,qman-channel-id = <0x29>;
408 fsl,qman-channel-id = <0x2a>;
414 fsl,qman-channel-id = <0x2b>;
420 fsl,qman-channel-id = <0x2c>;
426 fsl,qman-channel-id = <0x2d>;
432 fsl,qman-channel-id = <0x2e>;
438 fsl,qman-channel-id = <0x2f>;
448 bus-frequency = <0>; // Filled out by kernel.
450 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
451 reg = <0xf 0xfe000000 0 0x00001000>;
458 corenet-law@0 {
460 reg = <0x0 0x1000>;
466 reg = <0x8000 0x1000>;
472 reg = <0x9000 0x1000>;
478 reg = <0x10000 0x1000
479 0x11000 0x1000>;
486 reg = <0x18000 0x1000>;
493 compatible = "fsl,pamu-v1.0", "fsl,pamu";
494 reg = <0x20000 0x4000>;
496 24 2 0 0
501 clock-frequency = <0>;
503 #address-cells = <0>;
505 reg = <0x40000 0x40000>;
512 reg = <0x41600 0x200>;
513 msi-available-ranges = <0 0x100>;
515 0xe0 0 0 0
516 0xe1 0 0 0
517 0xe2 0 0 0
518 0xe3 0 0 0
519 0xe4 0 0 0
520 0xe5 0 0 0
521 0xe6 0 0 0
522 0xe7 0 0 0>;
527 reg = <0x41800 0x200>;
528 msi-available-ranges = <0 0x100>;
530 0xe8 0 0 0
531 0xe9 0 0 0
532 0xea 0 0 0
533 0xeb 0 0 0
534 0xec 0 0 0
535 0xed 0 0 0
536 0xee 0 0 0
537 0xef 0 0 0>;
542 reg = <0x41a00 0x200>;
543 msi-available-ranges = <0 0x100>;
545 0xf0 0 0 0
546 0xf1 0 0 0
547 0xf2 0 0 0
548 0xf3 0 0 0
549 0xf4 0 0 0
550 0xf5 0 0 0
551 0xf6 0 0 0
552 0xf7 0 0 0>;
557 reg = <0xe0000 0xe00>;
565 reg = <0xe0e00 0x200>;
571 reg = <0xe1000 0x1000>;
572 clock-frequency = <0>;
577 reg = <0xe2000 0x1000>;
583 reg = <0xe8000 0x1000>;
588 reg = <0xea000 0x1000>;
595 reg = <0x100300 0x4>;
596 ranges = <0x0 0x100100 0x200>;
597 cell-index = <0>;
598 dma-channel@0 {
601 reg = <0x0 0x80>;
602 cell-index = <0>;
603 interrupts = <28 2 0 0>;
608 reg = <0x80 0x80>;
610 interrupts = <29 2 0 0>;
615 reg = <0x100 0x80>;
617 interrupts = <30 2 0 0>;
622 reg = <0x180 0x80>;
624 interrupts = <31 2 0 0>;
632 reg = <0x101300 0x4>;
633 ranges = <0x0 0x101100 0x200>;
635 dma-channel@0 {
638 reg = <0x0 0x80>;
639 cell-index = <0>;
640 interrupts = <32 2 0 0>;
645 reg = <0x80 0x80>;
647 interrupts = <33 2 0 0>;
652 reg = <0x100 0x80>;
654 interrupts = <34 2 0 0>;
659 reg = <0x180 0x80>;
661 interrupts = <35 2 0 0>;
667 #size-cells = <0>;
669 reg = <0x110000 0x1000>;
670 interrupts = <53 0x2 0 0>;
676 reg = <0x114000 0x1000>;
677 interrupts = <48 2 0 0>;
679 clock-frequency = <0>;
684 #size-cells = <0>;
685 cell-index = <0>;
687 reg = <0x118000 0x100>;
688 interrupts = <38 2 0 0>;
694 #size-cells = <0>;
697 reg = <0x118100 0x100>;
698 interrupts = <38 2 0 0>;
704 #size-cells = <0>;
707 reg = <0x119000 0x100>;
708 interrupts = <39 2 0 0>;
714 #size-cells = <0>;
717 reg = <0x119100 0x100>;
718 interrupts = <39 2 0 0>;
723 cell-index = <0>;
726 reg = <0x11c500 0x100>;
727 clock-frequency = <0>;
728 interrupts = <36 2 0 0>;
735 reg = <0x11c600 0x100>;
736 clock-frequency = <0>;
737 interrupts = <36 2 0 0>;
744 reg = <0x11d500 0x100>;
745 clock-frequency = <0>;
746 interrupts = <37 2 0 0>;
753 reg = <0x11d600 0x100>;
754 clock-frequency = <0>;
755 interrupts = <37 2 0 0>;
760 reg = <0x130000 0x1000>;
761 interrupts = <55 2 0 0>;
770 ranges = <0x0 0x1e0000 0x20000>;
771 reg = <0x1e0000 0x20000>;
773 fsl,qman-channels-id = <0x62 0x63>;
775 inbound-block@0 {
777 reg = <0x0 0x800>;
781 reg = <0xb00 0x500>;
785 reg = <0x1000 0x800>;
789 reg = <0x2000 0x800>;
793 reg = <0x3000 0x800>;
800 reg = <0x210000 0x1000>;
802 #size-cells = <0>;
803 interrupts = <44 0x2 0 0>;
811 reg = <0x211000 0x1000>;
813 #size-cells = <0>;
814 interrupts = <45 0x2 0 0>;
821 reg = <0x220000 0x1000>;
822 interrupts = <68 0x2 0 0>;
827 reg = <0x221000 0x1000>;
828 interrupts = <69 0x2 0 0>;
832 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
835 reg = <0x300000 0x10000>;
836 ranges = <0 0x300000 0x10000>;
837 interrupts = <92 2 0 0>;
841 "fsl,sec-v4.0-job-ring";
842 reg = <0x1000 0x1000>;
843 interrupts = <88 2 0 0>;
848 "fsl,sec-v4.0-job-ring";
849 reg = <0x2000 0x1000>;
850 interrupts = <89 2 0 0>;
855 "fsl,sec-v4.0-job-ring";
856 reg = <0x3000 0x1000>;
857 interrupts = <90 2 0 0>;
862 "fsl,sec-v4.0-job-ring";
863 reg = <0x4000 0x1000>;
864 interrupts = <91 2 0 0>;
869 "fsl,sec-v4.0-rtic";
872 reg = <0x6000 0x100>;
873 ranges = <0x0 0x6100 0xe00>;
875 rtic_a: rtic-a@0 {
877 "fsl,sec-v4.0-rtic-memory";
878 reg = <0x00 0x20 0x100 0x80>;
883 "fsl,sec-v4.0-rtic-memory";
884 reg = <0x20 0x20 0x200 0x80>;
889 "fsl,sec-v4.0-rtic-memory";
890 reg = <0x40 0x20 0x300 0x80>;
895 "fsl,sec-v4.0-rtic-memory";
896 reg = <0x60 0x20 0x500 0x80>;
902 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
903 reg = <0x314000 0x1000>;
904 interrupts = <93 2 0 0>;
908 compatible = "fsl,raideng-v1.0";
911 reg = <0x320000 0x10000>;
912 ranges = <0 0x320000 0x10000>;
915 compatible = "fsl,raideng-v1.0-job-queue";
918 reg = <0x1000 0x1000>;
919 ranges = <0x0 0x1000 0x1000>;
921 raideng_jr0: jr@0 {
922 compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring";
923 reg = <0x0 0x400>;
924 interrupts = <139 2 0 0>;
929 compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-lp-ring";
930 reg = <0x400 0x400>;
931 interrupts = <140 2 0 0>;
937 compatible = "fsl,raideng-v1.0-job-queue";
940 reg = <0x2000 0x1000>;
941 ranges = <0x0 0x2000 0x1000>;
943 raideng_jr2: jr@0 {
944 compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring";
945 reg = <0x0 0x400>;
946 interrupts = <141 2 0 0>;
951 compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-lp-ring";
952 reg = <0x400 0x400>;
953 interrupts = <142 2 0 0>;
961 reg = <0x316000 0x10000>;
962 /* "fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */
963 /* "fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */
969 reg = <0x318000 0x1000>;
972 /* "fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */
973 /* "fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */
978 reg = <0x31a000 0x1000>;
981 /* "fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */
987 cell-index = <0>;
989 ranges = <0 0x400000 0x100000>;
990 reg = <0x400000 0x100000>;
991 clock-frequency = <0>;
993 96 2 0 0
996 cc@0 {
1002 reg = <0xc7000 0x1000>;
1007 reg = <0xc1000 0x1000>;
1012 reg = <0xc0000 0x1000>;
1015 muram@0 {
1017 reg = <0x0 0x28000>;
1022 reg = <0x80000 0x400>;
1027 reg = <0x80400 0x400>;
1031 cell-index = <0>;
1033 reg = <0x88000 0x1000>;
1038 reg = <0x89000 0x1000>;
1043 reg = <0x8a000 0x1000>;
1048 reg = <0x8b000 0x1000>;
1053 reg = <0x8c000 0x1000>;
1056 cell-index = <0>;
1058 reg = <0x90000 0x1000>;
1062 cell-index = <0>;
1064 reg = <0xb0000 0x1000>;
1065 fsl,qman-channel-id = <0x40>;
1068 cell-index = <0>;
1070 reg = <0xa8000 0x1000>;
1071 fsl,qman-channel-id = <0x41>;
1076 reg = <0xa9000 0x1000>;
1077 fsl,qman-channel-id = <0x42>;
1082 reg = <0xaa000 0x1000>;
1083 fsl,qman-channel-id = <0x43>;
1088 reg = <0xab000 0x1000>;
1089 fsl,qman-channel-id = <0x44>;
1094 reg = <0xac000 0x1000>;
1095 fsl,qman-channel-id = <0x45>;
1099 cell-index = <0>;
1101 reg = <0x81000 0x1000>;
1102 fsl,qman-channel-id = <0x46>;
1107 reg = <0x82000 0x1000>;
1108 fsl,qman-channel-id = <0x47>;
1113 reg = <0x83000 0x1000>;
1114 fsl,qman-channel-id = <0x48>;
1119 reg = <0x84000 0x1000>;
1120 fsl,qman-channel-id = <0x49>;
1125 reg = <0x85000 0x1000>;
1126 fsl,qman-channel-id = <0x4a>;
1131 reg = <0x86000 0x1000>;
1132 fsl,qman-channel-id = <0x4b>;
1137 reg = <0x87000 0x1000>;
1141 cell-index = <0>;
1143 reg = <0xe0000 0x1000>;
1150 #size-cells = <0>;
1152 reg = <0xe1120 0xee0>;
1153 interrupts = <100 1 0 0>;
1159 reg = <0xe2000 0x1000>;
1166 #size-cells = <0>;
1168 reg = <0xe3120 0xee0>;
1169 interrupts = <100 1 0 0>;
1175 reg = <0xe4000 0x1000>;
1182 #size-cells = <0>;
1184 reg = <0xe5120 0xee0>;
1185 interrupts = <100 1 0 0>;
1191 reg = <0xe6000 0x1000>;
1198 #size-cells = <0>;
1200 reg = <0xe7120 0xee0>;
1201 interrupts = <100 1 0 0>;
1207 reg = <0xe8000 0x1000>;
1214 #size-cells = <0>;
1216 reg = <0xe9120 0xee0>;
1217 interrupts = <100 1 0 0>;
1221 cell-index = <0>;
1223 reg = <0xf0000 0x1000>;
1229 #size-cells = <0>;
1231 reg = <0xf1000 0x1000>;
1232 interrupts = <100 1 0 0>;
1237 reg = <0xfe000 0x1000>;
1263 compatible = "fsl,p5020-rev1.0-elbc", "simple-bus", "fsl,elbc";
1265 25 2 0 0
1278 cell-index = <0>;
1279 bus-range = <0x0 0xff>;
1280 clock-frequency = <0x1fca055>;
1284 pcie@0 {
1285 reg = <0 0 0 0 0>;
1291 interrupt-map-mask = <0xf800 0 0 7>;
1293 /* IDSEL 0x0 */
1294 0000 0 0 1 &mpic 40 1 0 0
1295 0000 0 0 2 &mpic 1 1 0 0
1296 0000 0 0 3 &mpic 2 1 0 0
1297 0000 0 0 4 &mpic 3 1 0 0
1309 bus-range = <0 0xff>;
1310 clock-frequency = <0x1fca055>;
1313 pcie@0 {
1314 reg = <0 0 0 0 0>;
1320 interrupt-map-mask = <0xf800 0 0 7>;
1322 /* IDSEL 0x0 */
1323 0000 0 0 1 &mpic 41 1 0 0
1324 0000 0 0 2 &mpic 5 1 0 0
1325 0000 0 0 3 &mpic 6 1 0 0
1326 0000 0 0 4 &mpic 7 1 0 0
1338 bus-range = <0x0 0xff>;
1339 clock-frequency = <0x1fca055>;
1342 pcie@0 {
1343 reg = <0 0 0 0 0>;
1349 interrupt-map-mask = <0xf800 0 0 7>;
1351 /* IDSEL 0x0 */
1352 0000 0 0 1 &mpic 42 1 0 0
1353 0000 0 0 2 &mpic 9 1 0 0
1354 0000 0 0 3 &mpic 10 1 0 0
1355 0000 0 0 4 &mpic 11 1 0 0
1367 bus-range = <0x0 0xff>;
1368 clock-frequency = <0x1fca055>;
1371 pcie@0 {
1372 reg = <0 0 0 0 0>;
1378 interrupt-map-mask = <0xf800 0 0 7>;
1380 /* IDSEL 0x0 */
1381 0000 0 0 1 &mpic 43 1 0 0
1382 0000 0 0 2 &mpic 0 1 0 0
1383 0000 0 0 3 &mpic 4 1 0 0
1384 0000 0 0 4 &mpic 8 1 0 0