Lines Matching +full:qman +full:- +full:fqd
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
67 bman-portals@ff4000000 {
68 bman-portal@0 {
69 cpu-handle = <&cpu0>;
71 bman-portal@4000 {
72 cpu-handle = <&cpu1>;
74 bman-portal@8000 {
76 bman-portal@c000 {
78 bman-portal@10000 {
80 bman-portal@14000 {
82 bman-portal@18000 {
84 bman-portal@1c000 {
86 bman-portal@20000 {
88 bman-portal@24000 {
91 buffer-pool@0 {
92 compatible = "fsl,p5020-bpool", "fsl,bpool";
94 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
98 qman-portals@ff4200000 {
99 qportal0: qman-portal@0 {
100 cpu-handle = <&cpu0>;
101 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
108 qportal1: qman-portal@4000 {
109 cpu-handle = <&cpu1>;
110 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
117 qportal2: qman-portal@8000 {
118 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
125 qportal3: qman-portal@c000 {
126 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
133 qportal4: qman-portal@10000 {
134 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
141 qportal5: qman-portal@14000 {
142 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
149 qportal6: qman-portal@18000 {
150 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
157 qportal7: qman-portal@1c000 {
158 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
165 qportal8: qman-portal@20000 {
166 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
173 qportal9: qman-portal@24000 {
174 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
185 #address-cells = <1>;
186 #size-cells = <1>;
189 spi-max-frequency = <40000000>; /* input clock */
190 partition@u-boot {
191 label = "u-boot";
193 read-only;
198 read-only;
203 read-only;
233 /* fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */
234 /* fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */
237 qman: qman@318000 { label
239 /* fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */
240 /* fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */
244 /* Same as fsl,qman-*, use default allocation */
245 /* fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */
250 tbi-handle = <&tbi0>;
251 phy-handle = <&phy_rgmii_0>;
252 phy-connection-type = "rgmii";
256 tbi0: tbi-phy@8 {
258 device_type = "tbi-phy";
262 * Virtual MDIO for the two on-board RGMII
263 * ports. The fsl,hydra-mdio-muxval property
266 hydra_mdio_rgmii: hydra-mdio-rgmii {
267 #address-cells = <1>;
268 #size-cells = <0>;
269 compatible = "fsl,hydra-mdio";
270 fsl,mdio-handle = <&mdio0>;
271 fsl,hydra-mdio-muxval = <0x00>;
274 phy_rgmii_0: ethernet-phy@0 {
277 phy_rgmii_1: ethernet-phy@1 {
283 * Virtual MDIO for the four-port SGMII card.
284 * The fsl,hydra-mdio-muxval property will be
285 * fixed-up by U-Boot based on the slot that
291 hydra_mdio_sgmii: hydra-mdio-sgmii {
292 #address-cells = <1>;
293 #size-cells = <0>;
294 compatible = "fsl,hydra-mdio";
295 fsl,mdio-handle = <&mdio0>;
296 fsl,hydra-mdio-muxval = <0x00>;
299 phy_sgmii_1c: ethernet-phy@1c {
302 phy_sgmii_1d: ethernet-phy@1d {
305 phy_sgmii_1e: ethernet-phy@1e {
308 phy_sgmii_1f: ethernet-phy@1f {
315 tbi-handle = <&tbi1>;
316 phy-handle = <&phy_sgmii_1d>;
317 phy-connection-type = "sgmii";
321 tbi1: tbi-phy@8 {
323 device_type = "tbi-phy";
328 tbi-handle = <&tbi2>;
329 phy-handle = <&phy_sgmii_1e>;
330 phy-connection-type = "sgmii";
334 tbi2: tbi-phy@8 {
336 device_type = "tbi-phy";
341 tbi-handle = <&tbi3>;
342 phy-handle = <&phy_sgmii_1f>;
343 phy-connection-type = "sgmii";
347 #address-cells = <1>;
348 #size-cells = <0>;
349 compatible = "fsl,fman-tbi";
353 tbi3: tbi-phy@8 {
355 device_type = "tbi-phy";
360 tbi-handle = <&tbi4>;
361 phy-handle = <&phy_rgmii_1>;
362 phy-connection-type = "rgmii";
366 tbi4: tbi-phy@8 {
368 device_type = "tbi-phy";
374 * phy-handle will be updated by U-Boot to
377 phy-handle = <&phy_xgmii_1>;
378 phy-connection-type = "xgmii";
383 * is set by U-Boot, and Linux never touches it.
386 * only one of the ethernet-phy nodes below will be
393 phy_xgmii_1: ethernet-phy@4 {
398 phy_xgmii_2: ethernet-phy@0 {
421 compatible = "cfi-flash";
429 bank-width = <2>;
430 device-width = <2>;
434 #address-cells = <1>;
435 #size-cells = <1>;
436 compatible = "fsl,elbc-fcm-nand";
440 label = "NAND U-Boot Image";
442 read-only;
471 board-control@3,0 {
472 compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis";