Lines Matching +full:0 +full:x21000000
60 reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
64 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
68 bman-portal@0 {
91 buffer-pool@0 {
93 fsl,bpid = <0>;
94 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
99 qportal0: qman-portal@0 {
184 flash@0 {
188 reg = <0>;
192 reg = <0x00000000 0x00100000>;
197 reg = <0x00100000 0x00500000>;
202 reg = <0x00600000 0x00100000>;
207 reg = <0x00700000 0x00900000>;
215 reg = <0x51>;
219 reg = <0x52>;
226 reg = <0x68>;
227 interrupts = <0x1 0x1 0 0>;
233 /* fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */
234 /* fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */
239 /* fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */
240 /* fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */
245 /* fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */
257 reg = <0x8>;
268 #size-cells = <0>;
271 fsl,hydra-mdio-muxval = <0x00>;
274 phy_rgmii_0: ethernet-phy@0 {
275 reg = <0x0>;
278 reg = <0x1>;
293 #size-cells = <0>;
296 fsl,hydra-mdio-muxval = <0x00>;
300 reg = <0x1c>;
303 reg = <0x1d>;
306 reg = <0x1e>;
309 reg = <0x1f>;
348 #size-cells = <0>;
350 reg = <0xe7120 0xee0>;
351 interrupts = <100 1 0 0>;
394 reg = <0x4>;
398 phy_xgmii_2: ethernet-phy@0 {
399 reg = <0x0>;
406 reg = <0xf 0xfe0c0000 0 0x11000>;
409 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
412 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
417 reg = <0xf 0xfe124000 0 0x1000>;
418 ranges = <0 0 0xf 0xb8000000 0x04000000>;
420 flash@0,0 {
428 reg = <0 0 0x04000000>;
433 nand@2,0 {
437 reg = <0x2 0x0 0x40000>;
439 partition@0 {
441 reg = <0x0 0x02000000>;
447 reg = <0x02000000 0x10000000>;
452 reg = <0x12000000 0x08000000>;
457 reg = <0x1a000000 0x04000000>;
462 reg = <0x1e000000 0x01000000>;
467 reg = <0x1f000000 0x21000000>;
471 board-control@3,0 {
473 reg = <3 0 0x30>;
478 reg = <0xf 0xfe200000 0 0x1000>;
479 ranges = <0x02000000 0 0x80000000 0x0 0x80000000 0x0 0x10000000
480 0x01000000 0 0x00000000 0x0 0xff000000 0x0 0x00010000>;
481 pcie@0 {
482 ranges = <0x02000000 0 0x80000000
483 0x02000000 0 0x80000000
484 0 0x10000000
486 0x01000000 0 0x00000000
487 0x01000000 0 0xff000000
488 0 0x00010000>;
493 reg = <0xf 0xfe201000 0 0x1000>;
494 ranges = <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x10000000
495 0x01000000 0x0 0x00000000 0x0 0xff010000 0x0 0x00010000>;
496 pcie@0 {
497 ranges = <0x02000000 0 0x90000000
498 0x02000000 0 0x90000000
499 0 0x10000000
501 0x01000000 0 0x00000000
502 0x01000000 0 0xff010000
503 0 0x00010000>;
508 reg = <0xf 0xfe202000 0 0x1000>;
509 ranges = <0x02000000 0 0xa0000000 0x0 0xa0000000 0 0x10000000
510 0x01000000 0 0x00000000 0x0 0xff020000 0 0x00010000>;
511 pcie@0 {
512 ranges = <0x02000000 0 0xa0000000
513 0x02000000 0 0xa0000000
514 0 0x10000000
516 0x01000000 0 0x00000000
517 0x01000000 0 0xff020000
518 0 0x00010000>;
523 reg = <0xf 0xfe203000 0 0x1000>;
524 ranges = <0x02000000 0 0xb0000000 0x0 0xb0000000 0 0x08000000
525 0x01000000 0 0x00000000 0x0 0xff030000 0 0x00010000>;
526 pcie@0 {
527 ranges = <0x02000000 0 0xb0000000
528 0x02000000 0 0xb0000000
529 0 0x08000000
531 0x01000000 0 0x00000000
532 0x01000000 0 0xff030000
533 0 0x00010000>;