Lines Matching +full:0 +full:xa8000
103 #size-cells = <0>;
105 cpu0: PowerPC,e500mc@0 {
107 reg = <0>;
145 dcsr-epu@0 {
147 interrupts = <52 2 0 0
148 84 2 0 0
149 85 2 0 0>;
151 reg = <0x0 0x1000>;
155 reg = <0x1000 0x1000 0x1000000 0x8000>;
159 reg = <0x2000 0x1000>;
163 reg = <0x8000 0x1000 0xB0000 0x1000>;
167 reg = <0x9000 0x1000>;
171 reg = <0x11000 0x1000>;
176 reg = <0x12000 0x1000>;
180 reg = <0x18000 0x1000>;
184 reg = <0x22000 0x1000>;
189 reg = <0x40000 0x1000>;
194 reg = <0x41000 0x1000>;
199 reg = <0x42000 0x1000>;
204 reg = <0x43000 0x1000>;
209 #address-cells = <0x1>;
210 #size-cells = <0x1>;
212 ranges = <0x0 0xf 0xfde00000 0x200000>;
213 bman-portal@0 {
214 cell-index = <0x0>;
216 reg = <0x0 0x4000 0x100000 0x1000>;
217 interrupts = <105 2 0 0>;
220 cell-index = <0x1>;
222 reg = <0x4000 0x4000 0x101000 0x1000>;
223 interrupts = <107 2 0 0>;
228 reg = <0x8000 0x4000 0x102000 0x1000>;
229 interrupts = <109 2 0 0>;
232 cell-index = <0x3>;
234 reg = <0xc000 0x4000 0x103000 0x1000>;
235 interrupts = <111 2 0 0>;
238 cell-index = <0x4>;
240 reg = <0x10000 0x4000 0x104000 0x1000>;
241 interrupts = <113 2 0 0>;
244 cell-index = <0x5>;
246 reg = <0x14000 0x4000 0x105000 0x1000>;
247 interrupts = <115 2 0 0>;
250 cell-index = <0x6>;
252 reg = <0x18000 0x4000 0x106000 0x1000>;
253 interrupts = <117 2 0 0>;
256 cell-index = <0x7>;
258 reg = <0x1c000 0x4000 0x107000 0x1000>;
259 interrupts = <119 2 0 0>;
262 cell-index = <0x8>;
264 reg = <0x20000 0x4000 0x108000 0x1000>;
265 interrupts = <121 2 0 0>;
268 cell-index = <0x9>;
270 reg = <0x24000 0x4000 0x109000 0x1000>;
271 interrupts = <123 2 0 0>;
274 buffer-pool@0 {
276 fsl,bpid = <0>;
277 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
282 #address-cells = <0x1>;
283 #size-cells = <0x1>;
285 ranges = <0x0 0xf 0xfdc00000 0x200000>;
286 qportal0: qman-portal@0 {
287 cell-index = <0x0>;
289 reg = <0x0 0x4000 0x100000 0x1000>;
290 interrupts = <104 0x2 0 0>;
291 fsl,qman-channel-id = <0x0>;
295 cell-index = <0x1>;
297 reg = <0x4000 0x4000 0x101000 0x1000>;
298 interrupts = <106 0x2 0 0>;
299 fsl,qman-channel-id = <0x1>;
303 cell-index = <0x2>;
305 reg = <0x8000 0x4000 0x102000 0x1000>;
306 interrupts = <108 0x2 0 0>;
307 fsl,qman-channel-id = <0x2>;
311 cell-index = <0x3>;
313 reg = <0xc000 0x4000 0x103000 0x1000>;
314 interrupts = <110 0x2 0 0>;
315 fsl,qman-channel-id = <0x3>;
319 cell-index = <0x4>;
321 reg = <0x10000 0x4000 0x104000 0x1000>;
322 interrupts = <112 0x2 0 0>;
323 fsl,qman-channel-id = <0x4>;
327 cell-index = <0x5>;
329 reg = <0x14000 0x4000 0x105000 0x1000>;
330 interrupts = <114 0x2 0 0>;
331 fsl,qman-channel-id = <0x5>;
335 cell-index = <0x6>;
337 reg = <0x18000 0x4000 0x106000 0x1000>;
338 interrupts = <116 0x2 0 0>;
339 fsl,qman-channel-id = <0x6>;
343 cell-index = <0x7>;
345 reg = <0x1c000 0x4000 0x107000 0x1000>;
346 interrupts = <118 0x2 0 0>;
347 fsl,qman-channel-id = <0x7>;
351 cell-index = <0x8>;
353 reg = <0x20000 0x4000 0x108000 0x1000>;
354 interrupts = <120 0x2 0 0>;
355 fsl,qman-channel-id = <0x8>;
359 cell-index = <0x9>;
361 reg = <0x24000 0x4000 0x109000 0x1000>;
362 interrupts = <122 0x2 0 0>;
363 fsl,qman-channel-id = <0x9>;
369 fsl,qman-channel-id = <0x21>;
375 fsl,qman-channel-id = <0x22>;
381 fsl,qman-channel-id = <0x23>;
387 fsl,qman-channel-id = <0x24>;
393 fsl,qman-channel-id = <0x25>;
399 fsl,qman-channel-id = <0x26>;
405 fsl,qman-channel-id = <0x27>;
411 fsl,qman-channel-id = <0x28>;
417 fsl,qman-channel-id = <0x29>;
423 fsl,qman-channel-id = <0x2a>;
429 fsl,qman-channel-id = <0x2b>;
435 fsl,qman-channel-id = <0x2c>;
441 fsl,qman-channel-id = <0x2d>;
447 fsl,qman-channel-id = <0x2e>;
453 fsl,qman-channel-id = <0x2f>;
463 bus-frequency = <0>; // Filled out by kernel.
465 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
466 reg = <0xf 0xfe000000 0 0x00001000>;
473 corenet-law@0 {
475 reg = <0x0 0x1000>;
481 reg = <0x8000 0x1000>;
487 reg = <0x10000 0x1000>;
493 reg = <0x18000 0x1000>;
500 compatible = "fsl,pamu-v1.0", "fsl,pamu";
501 reg = <0x20000 0x4000>;
503 24 2 0 0
508 clock-frequency = <0>;
510 #address-cells = <0>;
512 reg = <0x40000 0x40000>;
519 reg = <0x41600 0x200>;
520 msi-available-ranges = <0 0x100>;
522 0xe0 0 0 0
523 0xe1 0 0 0
524 0xe2 0 0 0
525 0xe3 0 0 0
526 0xe4 0 0 0
527 0xe5 0 0 0
528 0xe6 0 0 0
529 0xe7 0 0 0>;
534 reg = <0x41800 0x200>;
535 msi-available-ranges = <0 0x100>;
537 0xe8 0 0 0
538 0xe9 0 0 0
539 0xea 0 0 0
540 0xeb 0 0 0
541 0xec 0 0 0
542 0xed 0 0 0
543 0xee 0 0 0
544 0xef 0 0 0>;
549 reg = <0x41a00 0x200>;
550 msi-available-ranges = <0 0x100>;
552 0xf0 0 0 0
553 0xf1 0 0 0
554 0xf2 0 0 0
555 0xf3 0 0 0
556 0xf4 0 0 0
557 0xf5 0 0 0
558 0xf6 0 0 0
559 0xf7 0 0 0>;
564 reg = <0xe0000 0xe00>;
572 reg = <0xe0e00 0x200>;
578 reg = <0xe1000 0x1000>;
579 clock-frequency = <0>;
584 reg = <0xe2000 0x1000>;
590 reg = <0xe8000 0x1000>;
595 reg = <0xea000 0x1000>;
602 reg = <0x100300 0x4>;
603 ranges = <0x0 0x100100 0x200>;
604 cell-index = <0>;
605 dma-channel@0 {
608 reg = <0x0 0x80>;
609 cell-index = <0>;
610 interrupts = <28 2 0 0>;
615 reg = <0x80 0x80>;
617 interrupts = <29 2 0 0>;
622 reg = <0x100 0x80>;
624 interrupts = <30 2 0 0>;
629 reg = <0x180 0x80>;
631 interrupts = <31 2 0 0>;
639 reg = <0x101300 0x4>;
640 ranges = <0x0 0x101100 0x200>;
642 dma-channel@0 {
645 reg = <0x0 0x80>;
646 cell-index = <0>;
647 interrupts = <32 2 0 0>;
652 reg = <0x80 0x80>;
654 interrupts = <33 2 0 0>;
659 reg = <0x100 0x80>;
661 interrupts = <34 2 0 0>;
666 reg = <0x180 0x80>;
668 interrupts = <35 2 0 0>;
674 #size-cells = <0>;
676 reg = <0x110000 0x1000>;
677 interrupts = <53 0x2 0 0>;
683 reg = <0x114000 0x1000>;
684 interrupts = <48 2 0 0>;
686 clock-frequency = <0>;
691 #size-cells = <0>;
692 cell-index = <0>;
694 reg = <0x118000 0x100>;
695 interrupts = <38 2 0 0>;
701 #size-cells = <0>;
704 reg = <0x118100 0x100>;
705 interrupts = <38 2 0 0>;
711 #size-cells = <0>;
714 reg = <0x119000 0x100>;
715 interrupts = <39 2 0 0>;
721 #size-cells = <0>;
724 reg = <0x119100 0x100>;
725 interrupts = <39 2 0 0>;
730 cell-index = <0>;
733 reg = <0x11c500 0x100>;
734 clock-frequency = <0>;
735 interrupts = <36 2 0 0>;
742 reg = <0x11c600 0x100>;
743 clock-frequency = <0>;
744 interrupts = <36 2 0 0>;
751 reg = <0x11d500 0x100>;
752 clock-frequency = <0>;
753 interrupts = <37 2 0 0>;
760 reg = <0x11d600 0x100>;
761 clock-frequency = <0>;
762 interrupts = <37 2 0 0>;
767 reg = <0x130000 0x1000>;
768 interrupts = <55 2 0 0>;
777 ranges = <0x0 0x1e0000 0x20000>;
778 reg = <0x1e0000 0x20000>;
780 fsl,qman-channels-id = <0x62 0x63>;
782 inbound-block@0 {
784 reg = <0x0 0x800>;
788 reg = <0xb00 0x500>;
792 reg = <0x1000 0x800>;
796 reg = <0x2000 0x800>;
800 reg = <0x3000 0x800>;
807 reg = <0x210000 0x1000>;
809 #size-cells = <0>;
810 interrupts = <44 0x2 0 0>;
818 reg = <0x211000 0x1000>;
820 #size-cells = <0>;
821 interrupts = <45 0x2 0 0>;
828 reg = <0x220000 0x1000>;
829 interrupts = <68 0x2 0 0>;
834 reg = <0x221000 0x1000>;
835 interrupts = <69 0x2 0 0>;
839 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
842 reg = <0x300000 0x10000>;
843 ranges = <0 0x300000 0x10000>;
844 interrupts = <92 2 0 0>;
848 "fsl,sec-v4.0-job-ring";
849 reg = <0x1000 0x1000>;
850 interrupts = <88 2 0 0>;
855 "fsl,sec-v4.0-job-ring";
856 reg = <0x2000 0x1000>;
857 interrupts = <89 2 0 0>;
862 "fsl,sec-v4.0-job-ring";
863 reg = <0x3000 0x1000>;
864 interrupts = <90 2 0 0>;
869 "fsl,sec-v4.0-job-ring";
870 reg = <0x4000 0x1000>;
871 interrupts = <91 2 0 0>;
876 "fsl,sec-v4.0-rtic";
879 reg = <0x6000 0x100>;
880 ranges = <0x0 0x6100 0xe00>;
882 rtic_a: rtic-a@0 {
884 "fsl,sec-v4.0-rtic-memory";
885 reg = <0x00 0x20 0x100 0x80>;
890 "fsl,sec-v4.0-rtic-memory";
891 reg = <0x20 0x20 0x200 0x80>;
896 "fsl,sec-v4.0-rtic-memory";
897 reg = <0x40 0x20 0x300 0x80>;
902 "fsl,sec-v4.0-rtic-memory";
903 reg = <0x60 0x20 0x500 0x80>;
909 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
910 reg = <0x314000 0x1000>;
911 interrupts = <93 2 0 0>;
916 reg = <0x316000 0x10000>;
917 /* "fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */
918 /* "fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */
924 reg = <0x318000 0x1000>;
927 /* "fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */
928 /* "fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */
933 reg = <0x31a000 0x1000>;
936 /* "fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */
942 cell-index = <0>;
944 ranges = <0 0x400000 0x100000>;
945 reg = <0x400000 0x100000>;
946 clock-frequency = <0>;
948 96 2 0 0
951 cc@0 {
957 reg = <0xc7000 0x1000>;
962 reg = <0xc1000 0x1000>;
967 reg = <0xc0000 0x1000>;
970 muram@0 {
972 reg = <0x0 0x28000>;
977 reg = <0x80000 0x400>;
982 reg = <0x80400 0x400>;
986 cell-index = <0>;
988 reg = <0x88000 0x1000>;
993 reg = <0x89000 0x1000>;
998 reg = <0x8a000 0x1000>;
1003 reg = <0x8b000 0x1000>;
1008 reg = <0x8c000 0x1000>;
1011 cell-index = <0>;
1013 reg = <0x90000 0x1000>;
1017 cell-index = <0>;
1019 reg = <0xb0000 0x1000>;
1020 fsl,qman-channel-id = <0x40>;
1023 cell-index = <0>;
1025 reg = <0xa8000 0x1000>;
1026 fsl,qman-channel-id = <0x41>;
1031 reg = <0xa9000 0x1000>;
1032 fsl,qman-channel-id = <0x42>;
1037 reg = <0xaa000 0x1000>;
1038 fsl,qman-channel-id = <0x43>;
1043 reg = <0xab000 0x1000>;
1044 fsl,qman-channel-id = <0x44>;
1049 reg = <0xac000 0x1000>;
1050 fsl,qman-channel-id = <0x45>;
1054 cell-index = <0>;
1056 reg = <0x81000 0x1000>;
1057 fsl,qman-channel-id = <0x46>;
1062 reg = <0x82000 0x1000>;
1063 fsl,qman-channel-id = <0x47>;
1068 reg = <0x83000 0x1000>;
1069 fsl,qman-channel-id = <0x48>;
1074 reg = <0x84000 0x1000>;
1075 fsl,qman-channel-id = <0x49>;
1080 reg = <0x85000 0x1000>;
1081 fsl,qman-channel-id = <0x4a>;
1086 reg = <0x86000 0x1000>;
1087 fsl,qman-channel-id = <0x4b>;
1092 reg = <0x87000 0x1000>;
1096 cell-index = <0>;
1099 reg = <0xe0000 0x1000>;
1106 #size-cells = <0>;
1108 reg = <0xe1120 0xee0>;
1109 interrupts = <100 1 0 0>;
1116 reg = <0xe2000 0x1000>;
1123 #size-cells = <0>;
1125 reg = <0xe3120 0xee0>;
1126 interrupts = <100 1 0 0>;
1133 reg = <0xe4000 0x1000>;
1140 #size-cells = <0>;
1142 reg = <0xe5120 0xee0>;
1143 interrupts = <100 1 0 0>;
1150 reg = <0xe6000 0x1000>;
1156 #size-cells = <0>;
1158 reg = <0xe7120 0xee0>;
1159 interrupts = <100 1 0 0>;
1166 reg = <0xe8000 0x1000>;
1173 #size-cells = <0>;
1175 reg = <0xe9120 0xee0>;
1176 interrupts = <100 1 0 0>;
1180 cell-index = <0>;
1183 reg = <0xf0000 0x1000>;
1189 #size-cells = <0>;
1191 reg = <0xf1000 0x1000>;
1192 interrupts = <100 1 0 0>;
1197 reg = <0xfe000 0x1000>;
1223 compatible = "fsl,p3041-rev1.0-elbc", "simple-bus", "fsl,elbc";
1225 25 2 0 0
1238 bus-range = <0x0 0xff>;
1239 clock-frequency = <0x1fca055>;
1243 pcie@0 {
1244 reg = <0 0 0 0 0>;
1250 interrupt-map-mask = <0xf800 0 0 7>;
1252 /* IDSEL 0x0 */
1253 0000 0 0 1 &mpic 40 1 0 0
1254 0000 0 0 2 &mpic 1 1 0 0
1255 0000 0 0 3 &mpic 2 1 0 0
1256 0000 0 0 4 &mpic 3 1 0 0
1267 bus-range = <0 0xff>;
1268 clock-frequency = <0x1fca055>;
1271 pcie@0 {
1272 reg = <0 0 0 0 0>;
1278 interrupt-map-mask = <0xf800 0 0 7>;
1280 /* IDSEL 0x0 */
1281 0000 0 0 1 &mpic 41 1 0 0
1282 0000 0 0 2 &mpic 5 1 0 0
1283 0000 0 0 3 &mpic 6 1 0 0
1284 0000 0 0 4 &mpic 7 1 0 0
1295 bus-range = <0x0 0xff>;
1296 clock-frequency = <0x1fca055>;
1299 pcie@0 {
1300 reg = <0 0 0 0 0>;
1306 interrupt-map-mask = <0xf800 0 0 7>;
1308 /* IDSEL 0x0 */
1309 0000 0 0 1 &mpic 42 1 0 0
1310 0000 0 0 2 &mpic 9 1 0 0
1311 0000 0 0 3 &mpic 10 1 0 0
1312 0000 0 0 4 &mpic 11 1 0 0
1323 bus-range = <0x0 0xff>;
1324 clock-frequency = <0x1fca055>;
1327 pcie@0 {
1328 reg = <0 0 0 0 0>;
1334 interrupt-map-mask = <0xf800 0 0 7>;
1336 /* IDSEL 0x0 */
1337 0000 0 0 1 &mpic 43 1 0 0
1338 0000 0 0 2 &mpic 0 1 0 0
1339 0000 0 0 3 &mpic 4 1 0 0
1340 0000 0 0 4 &mpic 8 1 0 0