Lines Matching +full:qman +full:- +full:portals
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
67 bman-portals@ff4000000 {
68 bman-portal@0 {
69 cpu-handle = <&cpu0>;
71 bman-portal@4000 {
72 cpu-handle = <&cpu1>;
74 bman-portal@8000 {
75 cpu-handle = <&cpu2>;
77 bman-portal@c000 {
78 cpu-handle = <&cpu3>;
80 bman-portal@10000 {
82 bman-portal@14000 {
84 bman-portal@18000 {
86 bman-portal@1c000 {
88 bman-portal@20000 {
90 bman-portal@24000 {
93 buffer-pool@0 {
94 compatible = "fsl,p3041-bpool", "fsl,bpool";
96 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
100 qman-portals@ff4200000 {
101 qportal0: qman-portal@0 {
102 cpu-handle = <&cpu0>;
103 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
110 qportal1: qman-portal@4000 {
111 cpu-handle = <&cpu1>;
112 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
119 qportal2: qman-portal@8000 {
120 cpu-handle = <&cpu2>;
121 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
128 qportal3: qman-portal@c000 {
129 cpu-handle = <&cpu3>;
130 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
137 qportal4: qman-portal@10000 {
138 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
145 qportal5: qman-portal@14000 {
146 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
153 qportal6: qman-portal@18000 {
154 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
161 qportal7: qman-portal@1c000 {
162 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
169 qportal8: qman-portal@20000 {
170 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
177 qportal9: qman-portal@24000 {
178 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
189 #address-cells = <1>;
190 #size-cells = <1>;
193 spi-max-frequency = <35000000>; /* input clock */
194 partition@u-boot {
195 label = "u-boot";
197 read-only;
202 read-only;
207 read-only;
237 /* fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */
238 /* fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */
241 qman: qman@318000 { label
243 /* fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */
244 /* fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */
248 /* Same as fsl,qman-*, use default allocation */
249 /* fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */
254 tbi-handle = <&tbi0>;
255 phy-handle = <&phy_rgmii_0>;
256 phy-connection-type = "rgmii";
260 tbi0: tbi-phy@8 {
262 device_type = "tbi-phy";
266 * Virtual MDIO for the two on-board RGMII
267 * ports. The fsl,hydra-mdio-muxval property
270 hydra_mdio_rgmii: hydra-mdio-rgmii {
271 #address-cells = <1>;
272 #size-cells = <0>;
273 compatible = "fsl,hydra-mdio";
274 fsl,mdio-handle = <&mdio0>;
275 fsl,hydra-mdio-muxval = <0x00>;
278 phy_rgmii_0: ethernet-phy@0 {
281 phy_rgmii_1: ethernet-phy@1 {
287 * Virtual MDIO for the four-port SGMII card.
288 * The fsl,hydra-mdio-muxval property will be
289 * fixed-up by U-Boot based on the slot that
295 hydra_mdio_sgmii: hydra-mdio-sgmii {
296 #address-cells = <1>;
297 #size-cells = <0>;
298 compatible = "fsl,hydra-mdio";
299 fsl,mdio-handle = <&mdio0>;
300 fsl,hydra-mdio-muxval = <0x00>;
303 phy_sgmii_1c: ethernet-phy@1c {
306 phy_sgmii_1d: ethernet-phy@1d {
309 phy_sgmii_1e: ethernet-phy@1e {
312 phy_sgmii_1f: ethernet-phy@1f {
319 tbi-handle = <&tbi1>;
320 phy-handle = <&phy_sgmii_1d>;
321 phy-connection-type = "sgmii";
325 tbi1: tbi-phy@8 {
327 device_type = "tbi-phy";
332 tbi-handle = <&tbi2>;
333 phy-handle = <&phy_sgmii_1e>;
334 phy-connection-type = "sgmii";
338 tbi2: tbi-phy@8 {
340 device_type = "tbi-phy";
345 tbi-handle = <&tbi3>;
346 phy-handle = <&phy_sgmii_1f>;
347 phy-connection-type = "sgmii";
351 #address-cells = <1>;
352 #size-cells = <0>;
353 compatible = "fsl,fman-tbi";
357 tbi3: tbi-phy@8 {
359 device_type = "tbi-phy";
364 tbi-handle = <&tbi4>;
365 phy-handle = <&phy_rgmii_1>;
366 phy-connection-type = "rgmii";
370 tbi4: tbi-phy@8 {
372 device_type = "tbi-phy";
378 * phy-handle will be updated by U-Boot to
381 phy-handle = <&phy_xgmii_1>;
382 phy-connection-type = "xgmii";
387 * is set by U-Boot, and Linux never touches it.
390 * only one of the ethernet-phy nodes below will be
397 phy_xgmii_1: ethernet-phy@4 {
402 phy_xgmii_2: ethernet-phy@0 {
425 compatible = "cfi-flash";
433 bank-width = <2>;
434 device-width = <2>;
438 #address-cells = <1>;
439 #size-cells = <1>;
440 compatible = "fsl,elbc-fcm-nand";
444 label = "NAND U-Boot Image";
446 read-only;
475 board-control@3,0 {
476 compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis";