Lines Matching +full:0 +full:x220000
102 #size-cells = <0>;
104 cpu0: PowerPC,e500mc@0 {
106 reg = <0>;
144 dcsr-epu@0 {
146 interrupts = <52 2 0 0
147 84 2 0 0
148 85 2 0 0>;
150 reg = <0x0 0x1000>;
154 reg = <0x1000 0x1000 0x1000000 0x8000>;
158 reg = <0x2000 0x1000>;
162 reg = <0x8000 0x1000 0xB0000 0x1000>;
166 reg = <0x9000 0x1000>;
170 reg = <0x11000 0x1000>;
175 reg = <0x12000 0x1000>;
179 reg = <0x18000 0x1000>;
183 reg = <0x22000 0x1000>;
188 reg = <0x40000 0x1000>;
193 reg = <0x41000 0x1000>;
198 reg = <0x42000 0x1000>;
203 reg = <0x43000 0x1000>;
208 #address-cells = <0x1>;
209 #size-cells = <0x1>;
211 ranges = <0x0 0xf 0xfde00000 0x200000>;
212 bman-portal@0 {
213 cell-index = <0x0>;
215 reg = <0x0 0x4000 0x100000 0x1000>;
216 interrupts = <105 2 0 0>;
219 cell-index = <0x1>;
221 reg = <0x4000 0x4000 0x101000 0x1000>;
222 interrupts = <107 2 0 0>;
227 reg = <0x8000 0x4000 0x102000 0x1000>;
228 interrupts = <109 2 0 0>;
231 cell-index = <0x3>;
233 reg = <0xc000 0x4000 0x103000 0x1000>;
234 interrupts = <111 2 0 0>;
237 cell-index = <0x4>;
239 reg = <0x10000 0x4000 0x104000 0x1000>;
240 interrupts = <113 2 0 0>;
243 cell-index = <0x5>;
245 reg = <0x14000 0x4000 0x105000 0x1000>;
246 interrupts = <115 2 0 0>;
249 cell-index = <0x6>;
251 reg = <0x18000 0x4000 0x106000 0x1000>;
252 interrupts = <117 2 0 0>;
255 cell-index = <0x7>;
257 reg = <0x1c000 0x4000 0x107000 0x1000>;
258 interrupts = <119 2 0 0>;
261 cell-index = <0x8>;
263 reg = <0x20000 0x4000 0x108000 0x1000>;
264 interrupts = <121 2 0 0>;
267 cell-index = <0x9>;
269 reg = <0x24000 0x4000 0x109000 0x1000>;
270 interrupts = <123 2 0 0>;
273 buffer-pool@0 {
275 fsl,bpid = <0>;
276 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
281 #address-cells = <0x1>;
282 #size-cells = <0x1>;
284 ranges = <0x0 0xf 0xfdc00000 0x200000>;
285 qportal0: qman-portal@0 {
286 cell-index = <0x0>;
288 reg = <0x0 0x4000 0x100000 0x1000>;
289 interrupts = <104 0x2 0 0>;
290 fsl,qman-channel-id = <0x0>;
294 cell-index = <0x1>;
296 reg = <0x4000 0x4000 0x101000 0x1000>;
297 interrupts = <106 0x2 0 0>;
298 fsl,qman-channel-id = <0x1>;
302 cell-index = <0x2>;
304 reg = <0x8000 0x4000 0x102000 0x1000>;
305 interrupts = <108 0x2 0 0>;
306 fsl,qman-channel-id = <0x2>;
310 cell-index = <0x3>;
312 reg = <0xc000 0x4000 0x103000 0x1000>;
313 interrupts = <110 0x2 0 0>;
314 fsl,qman-channel-id = <0x3>;
318 cell-index = <0x4>;
320 reg = <0x10000 0x4000 0x104000 0x1000>;
321 interrupts = <112 0x2 0 0>;
322 fsl,qman-channel-id = <0x4>;
326 cell-index = <0x5>;
328 reg = <0x14000 0x4000 0x105000 0x1000>;
329 interrupts = <114 0x2 0 0>;
330 fsl,qman-channel-id = <0x5>;
334 cell-index = <0x6>;
336 reg = <0x18000 0x4000 0x106000 0x1000>;
337 interrupts = <116 0x2 0 0>;
338 fsl,qman-channel-id = <0x6>;
342 cell-index = <0x7>;
344 reg = <0x1c000 0x4000 0x107000 0x1000>;
345 interrupts = <118 0x2 0 0>;
346 fsl,qman-channel-id = <0x7>;
350 cell-index = <0x8>;
352 reg = <0x20000 0x4000 0x108000 0x1000>;
353 interrupts = <120 0x2 0 0>;
354 fsl,qman-channel-id = <0x8>;
358 cell-index = <0x9>;
360 reg = <0x24000 0x4000 0x109000 0x1000>;
361 interrupts = <122 0x2 0 0>;
362 fsl,qman-channel-id = <0x9>;
368 fsl,qman-channel-id = <0x21>;
374 fsl,qman-channel-id = <0x22>;
380 fsl,qman-channel-id = <0x23>;
386 fsl,qman-channel-id = <0x24>;
392 fsl,qman-channel-id = <0x25>;
398 fsl,qman-channel-id = <0x26>;
404 fsl,qman-channel-id = <0x27>;
410 fsl,qman-channel-id = <0x28>;
416 fsl,qman-channel-id = <0x29>;
422 fsl,qman-channel-id = <0x2a>;
428 fsl,qman-channel-id = <0x2b>;
434 fsl,qman-channel-id = <0x2c>;
440 fsl,qman-channel-id = <0x2d>;
446 fsl,qman-channel-id = <0x2e>;
452 fsl,qman-channel-id = <0x2f>;
462 bus-frequency = <0>; // Filled out by kernel.
464 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
465 reg = <0xf 0xfe000000 0 0x00001000>;
472 corenet-law@0 {
474 reg = <0x0 0x1000>;
480 reg = <0x8000 0x1000>;
486 reg = <0x10000 0x1000>;
492 reg = <0x18000 0x1000>;
499 compatible = "fsl,pamu-v1.0", "fsl,pamu";
500 reg = <0x20000 0x4000>;
502 24 2 0 0
507 clock-frequency = <0>;
509 #address-cells = <0>;
511 reg = <0x40000 0x40000>;
518 reg = <0x41600 0x200>;
519 msi-available-ranges = <0 0x100>;
521 0xe0 0 0 0
522 0xe1 0 0 0
523 0xe2 0 0 0
524 0xe3 0 0 0
525 0xe4 0 0 0
526 0xe5 0 0 0
527 0xe6 0 0 0
528 0xe7 0 0 0>;
533 reg = <0x41800 0x200>;
534 msi-available-ranges = <0 0x100>;
536 0xe8 0 0 0
537 0xe9 0 0 0
538 0xea 0 0 0
539 0xeb 0 0 0
540 0xec 0 0 0
541 0xed 0 0 0
542 0xee 0 0 0
543 0xef 0 0 0>;
548 reg = <0x41a00 0x200>;
549 msi-available-ranges = <0 0x100>;
551 0xf0 0 0 0
552 0xf1 0 0 0
553 0xf2 0 0 0
554 0xf3 0 0 0
555 0xf4 0 0 0
556 0xf5 0 0 0
557 0xf6 0 0 0
558 0xf7 0 0 0>;
563 reg = <0xe0000 0xe00>;
571 reg = <0xe0e00 0x200>;
577 reg = <0xe1000 0x1000>;
578 clock-frequency = <0>;
583 reg = <0xe2000 0x1000>;
589 reg = <0xe8000 0x1000>;
594 reg = <0xea000 0x1000>;
601 reg = <0x100300 0x4>;
602 ranges = <0x0 0x100100 0x200>;
603 cell-index = <0>;
604 dma-channel@0 {
607 reg = <0x0 0x80>;
608 cell-index = <0>;
609 interrupts = <28 2 0 0>;
614 reg = <0x80 0x80>;
616 interrupts = <29 2 0 0>;
621 reg = <0x100 0x80>;
623 interrupts = <30 2 0 0>;
628 reg = <0x180 0x80>;
630 interrupts = <31 2 0 0>;
638 reg = <0x101300 0x4>;
639 ranges = <0x0 0x101100 0x200>;
641 dma-channel@0 {
644 reg = <0x0 0x80>;
645 cell-index = <0>;
646 interrupts = <32 2 0 0>;
651 reg = <0x80 0x80>;
653 interrupts = <33 2 0 0>;
658 reg = <0x100 0x80>;
660 interrupts = <34 2 0 0>;
665 reg = <0x180 0x80>;
667 interrupts = <35 2 0 0>;
673 #size-cells = <0>;
675 reg = <0x110000 0x1000>;
676 interrupts = <53 0x2 0 0>;
682 reg = <0x114000 0x1000>;
683 interrupts = <48 2 0 0>;
685 clock-frequency = <0>;
690 #size-cells = <0>;
691 cell-index = <0>;
693 reg = <0x118000 0x100>;
694 interrupts = <38 2 0 0>;
700 #size-cells = <0>;
703 reg = <0x118100 0x100>;
704 interrupts = <38 2 0 0>;
710 #size-cells = <0>;
713 reg = <0x119000 0x100>;
714 interrupts = <39 2 0 0>;
720 #size-cells = <0>;
723 reg = <0x119100 0x100>;
724 interrupts = <39 2 0 0>;
729 cell-index = <0>;
732 reg = <0x11c500 0x100>;
733 clock-frequency = <0>;
734 interrupts = <36 2 0 0>;
741 reg = <0x11c600 0x100>;
742 clock-frequency = <0>;
743 interrupts = <36 2 0 0>;
750 reg = <0x11d500 0x100>;
751 clock-frequency = <0>;
752 interrupts = <37 2 0 0>;
759 reg = <0x11d600 0x100>;
760 clock-frequency = <0>;
761 interrupts = <37 2 0 0>;
766 reg = <0x130000 0x1000>;
767 interrupts = <55 2 0 0>;
776 ranges = <0x0 0x1e0000 0x20000>;
777 reg = <0x1e0000 0x20000>;
779 fsl,qman-channels-id = <0x62 0x63>;
781 inbound-block@0 {
783 reg = <0x0 0x800>;
787 reg = <0xb00 0x500>;
791 reg = <0x1000 0x800>;
795 reg = <0x2000 0x800>;
799 reg = <0x3000 0x800>;
806 reg = <0x210000 0x1000>;
808 #size-cells = <0>;
809 interrupts = <44 0x2 0 0>;
817 reg = <0x211000 0x1000>;
819 #size-cells = <0>;
820 interrupts = <45 0x2 0 0>;
826 reg = <0x220000 0x1000>;
827 interrupts = <68 0x2 0 0>;
832 reg = <0x221000 0x1000>;
833 interrupts = <69 0x2 0 0>;
837 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
840 reg = <0x300000 0x10000>;
841 ranges = <0 0x300000 0x10000>;
842 interrupts = <92 2 0 0>;
846 "fsl,sec-v4.0-job-ring";
847 reg = <0x1000 0x1000>;
848 interrupts = <88 2 0 0>;
853 "fsl,sec-v4.0-job-ring";
854 reg = <0x2000 0x1000>;
855 interrupts = <89 2 0 0>;
860 "fsl,sec-v4.0-job-ring";
861 reg = <0x3000 0x1000>;
862 interrupts = <90 2 0 0>;
867 "fsl,sec-v4.0-job-ring";
868 reg = <0x4000 0x1000>;
869 interrupts = <91 2 0 0>;
874 "fsl,sec-v4.0-rtic";
877 reg = <0x6000 0x100>;
878 ranges = <0x0 0x6100 0xe00>;
880 rtic_a: rtic-a@0 {
882 "fsl,sec-v4.0-rtic-memory";
883 reg = <0x00 0x20 0x100 0x80>;
888 "fsl,sec-v4.0-rtic-memory";
889 reg = <0x20 0x20 0x200 0x80>;
894 "fsl,sec-v4.0-rtic-memory";
895 reg = <0x40 0x20 0x300 0x80>;
900 "fsl,sec-v4.0-rtic-memory";
901 reg = <0x60 0x20 0x500 0x80>;
907 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
908 reg = <0x314000 0x1000>;
909 interrupts = <93 2 0 0>;
914 reg = <0x316000 0x10000>;
915 /* "fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */
916 /* "fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */
922 reg = <0x318000 0x1000>;
925 /* "fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */
926 /* "fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */
931 reg = <0x31a000 0x1000>;
934 /* "fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */
940 cell-index = <0>;
942 ranges = <0 0x400000 0x100000>;
943 reg = <0x400000 0x100000>;
944 clock-frequency = <0>;
946 96 2 0 0
949 cc@0 {
955 reg = <0xc7000 0x1000>;
960 reg = <0xc1000 0x1000>;
965 reg = <0xc0000 0x1000>;
968 muram@0 {
970 reg = <0x0 0x28000>;
975 reg = <0x80000 0x400>;
980 reg = <0x80400 0x400>;
984 cell-index = <0>;
986 reg = <0x88000 0x1000>;
991 reg = <0x89000 0x1000>;
996 reg = <0x8a000 0x1000>;
1001 reg = <0x8b000 0x1000>;
1006 reg = <0x8c000 0x1000>;
1009 cell-index = <0>;
1011 reg = <0x90000 0x1000>;
1015 cell-index = <0>;
1017 reg = <0xb0000 0x1000>;
1018 fsl,qman-channel-id = <0x40>;
1021 cell-index = <0>;
1023 reg = <0xa8000 0x1000>;
1024 fsl,qman-channel-id = <0x41>;
1029 reg = <0xa9000 0x1000>;
1030 fsl,qman-channel-id = <0x42>;
1035 reg = <0xaa000 0x1000>;
1036 fsl,qman-channel-id = <0x43>;
1041 reg = <0xab000 0x1000>;
1042 fsl,qman-channel-id = <0x44>;
1047 reg = <0xac000 0x1000>;
1048 fsl,qman-channel-id = <0x45>;
1052 cell-index = <0>;
1054 reg = <0x81000 0x1000>;
1055 fsl,qman-channel-id = <0x46>;
1060 reg = <0x82000 0x1000>;
1061 fsl,qman-channel-id = <0x47>;
1066 reg = <0x83000 0x1000>;
1067 fsl,qman-channel-id = <0x48>;
1072 reg = <0x84000 0x1000>;
1073 fsl,qman-channel-id = <0x49>;
1078 reg = <0x85000 0x1000>;
1079 fsl,qman-channel-id = <0x4a>;
1084 reg = <0x86000 0x1000>;
1085 fsl,qman-channel-id = <0x4b>;
1090 reg = <0x87000 0x1000>;
1094 cell-index = <0>;
1096 reg = <0xe0000 0x1000>;
1102 #size-cells = <0>;
1104 reg = <0xe1120 0xee0>;
1105 interrupts = <100 1 0 0>;
1111 reg = <0xe2000 0x1000>;
1117 #size-cells = <0>;
1119 reg = <0xe3120 0xee0>;
1120 interrupts = <100 1 0 0>;
1126 reg = <0xe4000 0x1000>;
1132 #size-cells = <0>;
1134 reg = <0xe5120 0xee0>;
1135 interrupts = <100 1 0 0>;
1141 reg = <0xe6000 0x1000>;
1147 #size-cells = <0>;
1149 reg = <0xe7120 0xee0>;
1150 interrupts = <100 1 0 0>;
1156 reg = <0xe8000 0x1000>;
1162 #size-cells = <0>;
1164 reg = <0xe9120 0xee0>;
1165 interrupts = <100 1 0 0>;
1169 cell-index = <0>;
1171 reg = <0xf0000 0x1000>;
1177 #size-cells = <0>;
1179 reg = <0xf1000 0x1000>;
1180 interrupts = <100 1 0 0>;
1207 interrupts = <25 2 0 0>;
1218 bus-range = <0x0 0xff>;
1222 pcie@0 {
1223 reg = <0 0 0 0 0>;
1229 interrupt-map-mask = <0xf800 0 0 7>;
1231 /* IDSEL 0x0 */
1232 0000 0 0 1 &mpic 40 1 0 0
1233 0000 0 0 2 &mpic 1 1 0 0
1234 0000 0 0 3 &mpic 2 1 0 0
1235 0000 0 0 4 &mpic 3 1 0 0
1246 bus-range = <0 0xff>;
1250 pcie@0 {
1251 reg = <0 0 0 0 0>;
1257 interrupt-map-mask = <0xf800 0 0 7>;
1259 /* IDSEL 0x0 */
1260 0000 0 0 1 &mpic 41 1 0 0
1261 0000 0 0 2 &mpic 5 1 0 0
1262 0000 0 0 3 &mpic 6 1 0 0
1263 0000 0 0 4 &mpic 7 1 0 0
1274 bus-range = <0x0 0xff>;
1278 pcie@0 {
1279 reg = <0 0 0 0 0>;
1285 interrupt-map-mask = <0xf800 0 0 7>;
1287 /* IDSEL 0x0 */
1288 0000 0 0 1 &mpic 42 1 0 0
1289 0000 0 0 2 &mpic 9 1 0 0
1290 0000 0 0 3 &mpic 10 1 0 0
1291 0000 0 0 4 &mpic 11 1 0 0