Lines Matching +full:qman +full:- +full:portals
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
66 bman-portals@ff4000000 {
67 bman-portal@0 {
68 cpu-handle = <&cpu0>;
70 bman-portal@4000 {
71 cpu-handle = <&cpu1>;
73 bman-portal@8000 {
74 cpu-handle = <&cpu2>;
76 bman-portal@c000 {
77 cpu-handle = <&cpu3>;
79 bman-portal@10000 {
81 bman-portal@14000 {
83 bman-portal@18000 {
85 bman-portal@1c000 {
87 bman-portal@20000 {
89 bman-portal@24000 {
92 buffer-pool@0 {
93 compatible = "fsl,p2041-bpool", "fsl,bpool";
95 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
99 qman-portals@ff4200000 {
100 qportal0: qman-portal@0 {
101 cpu-handle = <&cpu0>;
102 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
109 qportal1: qman-portal@4000 {
110 cpu-handle = <&cpu1>;
111 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
118 qportal2: qman-portal@8000 {
119 cpu-handle = <&cpu2>;
120 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
127 qportal3: qman-portal@c000 {
128 cpu-handle = <&cpu3>;
129 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
136 qportal4: qman-portal@10000 {
137 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
144 qportal5: qman-portal@14000 {
145 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
152 qportal6: qman-portal@18000 {
153 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
160 qportal7: qman-portal@1c000 {
161 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
168 qportal8: qman-portal@20000 {
169 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
176 qportal9: qman-portal@24000 {
177 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
188 #address-cells = <1>;
189 #size-cells = <1>;
192 spi-max-frequency = <40000000>; /* input clock */
193 partition@u-boot {
194 label = "u-boot";
196 read-only;
201 read-only;
206 read-only;
243 /* fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */
244 /* fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */
247 qman: qman@318000 { label
249 /* fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */
250 /* fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */
254 /* Same as fsl,qman-*, use default allocation */
255 /* fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */
260 tbi-handle = <&tbi0>;
261 phy-handle = <&phy_sgmii_2>;
262 phy-connection-type = "sgmii";
266 tbi0: tbi-phy@8 {
268 device_type = "tbi-phy";
271 phy_rgmii_0: ethernet-phy@0 {
274 phy_rgmii_1: ethernet-phy@1 {
277 phy_sgmii_2: ethernet-phy@2 {
280 phy_sgmii_3: ethernet-phy@3 {
283 phy_sgmii_4: ethernet-phy@4 {
286 phy_sgmii_1c: ethernet-phy@1c {
289 phy_sgmii_1d: ethernet-phy@1d {
292 phy_sgmii_1e: ethernet-phy@1e {
295 phy_sgmii_1f: ethernet-phy@1f {
301 tbi-handle = <&tbi1>;
302 phy-handle = <&phy_sgmii_3>;
303 phy-connection-type = "sgmii";
307 tbi1: tbi-phy@8 {
309 device_type = "tbi-phy";
314 tbi-handle = <&tbi2>;
315 phy-handle = <&phy_sgmii_4>;
316 phy-connection-type = "sgmii";
320 tbi2: tbi-phy@8 {
322 device_type = "tbi-phy";
327 tbi-handle = <&tbi3>;
328 phy-handle = <&phy_rgmii_1>;
329 phy-connection-type = "rgmii";
333 tbi3: tbi-phy@8 {
335 device_type = "tbi-phy";
340 tbi-handle = <&tbi4>;
341 phy-handle = <&phy_rgmii_0>;
342 phy-connection-type = "rgmii";
346 tbi4: tbi-phy@8 {
348 device_type = "tbi-phy";
354 * phy-handle will be updated by U-Boot to
357 phy-handle = <&phy_xgmii_2>;
358 phy-connection-type = "xgmii";
363 phy_xgmii_2: ethernet-phy@0 {
386 compatible = "cfi-flash";
394 bank-width = <2>;
395 device-width = <2>;