Lines Matching +full:0 +full:xfee00000
80 #size-cells = <0>;
82 PowerPC,8555@0 {
84 reg = <0x0>;
87 d-cache-size = <0x8000>; // L1, 32K
88 i-cache-size = <0x8000>; // L1, 32K
89 timebase-frequency = <0>; // 33 MHz, from uboot
90 bus-frequency = <0>; // 166 MHz
91 clock-frequency = <0>; // 825 MHz, from uboot
98 reg = <0x0 0x10000000>; // 256M at 0x0
105 reg = <0xe0005000 0x1000>;
109 ranges = <0x0 0x0 0xff800000 0x00800000
110 0x1 0x0 0xff000000 0x00800000
111 0x2 0x0 0xf8000000 0x00008000>;
113 nor@0,0 {
117 reg = <0x0 0x0 0x00800000>;
122 nor@1,0 {
126 reg = <0x1 0x0 0x00800000>;
131 rtc@2,0 {
135 reg = <0x2 0x0 0x00008000>;
146 ranges = <0x0 0xe0000000 0x100000>;
147 bus-frequency = <0>;
149 ecm-law@0 {
151 reg = <0x0 0x1000>;
157 reg = <0x1000 0x1000>;
164 reg = <0x2000 0x1000>;
171 reg = <0x20000 0x1000>;
173 cache-size = <0x40000>; // L2, 256K
180 #size-cells = <0>;
181 cell-index = <0>;
183 reg = <0x3000 0x100>;
193 reg = <0x21300 0x4>;
194 ranges = <0x0 0x21100 0x200>;
195 cell-index = <0>;
196 dma-channel@0 {
199 reg = <0x0 0x80>;
200 cell-index = <0>;
207 reg = <0x80 0x80>;
215 reg = <0x100 0x80>;
223 reg = <0x180 0x80>;
233 cell-index = <0>;
237 reg = <0x24000 0x1000>;
238 ranges = <0x0 0x24000 0x1000>;
247 #size-cells = <0>;
249 reg = <0x520 0x20>;
251 phy0: ethernet-phy@0 {
254 reg = <0x0>;
260 reg = <0x1>;
264 reg = <0x11>;
277 reg = <0x25000 0x1000>;
278 ranges = <0x0 0x25000 0x1000>;
287 #size-cells = <0>;
289 reg = <0x520 0x20>;
292 reg = <0x11>;
299 cell-index = <0>;
302 reg = <0x4500 0x100>; // reg base, size
303 clock-frequency = <0>; // should we fill in in uboot?
312 reg = <0x4600 0x100>; // reg base, size
313 clock-frequency = <0>; // should we fill in in uboot?
319 compatible = "fsl,sec2.0";
320 reg = <0x30000 0x10000>;
325 fsl,exec-units-mask = <0x7e>;
326 fsl,descriptor-types-mask = <0x01010ebf>;
331 #address-cells = <0>;
333 reg = <0x40000 0x40000>;
342 reg = <0x80000 0x20000>;
349 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
352 /* IDSEL 0x10 */
353 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
354 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
355 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
356 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
358 /* IDSEL 0x11 */
359 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
360 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
361 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
362 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
364 /* IDSEL 0x12 (Slot 1) */
365 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
366 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
367 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
368 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
370 /* IDSEL 0x13 (Slot 2) */
371 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
372 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
373 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
374 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
376 /* IDSEL 0x14 (Slot 3) */
377 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
378 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
379 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
380 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
382 /* IDSEL 0x15 (Slot 4) */
383 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
384 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
385 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
386 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
389 /* IDSEL 0x12 (ISA bridge) */
390 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
391 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
392 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
393 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
396 bus-range = <0 0>;
397 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
398 0x1000000 0x0 0x0 0xfee00000 0x0 0x00010000>;
403 reg = <0xe0008000 0x1000>;
410 reg = <0x19000 0x0 0x0 0x0 0x1>;
411 #address-cells = <0>;
420 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
423 /* IDSEL 0x15 */
424 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
425 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
426 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
427 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
430 bus-range = <0 0>;
431 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
432 0x1000000 0x0 0x0 0xfee10000 0x0 0x00010000>;
437 reg = <0xe0009000 0x1000>;