Lines Matching +full:tegra20 +full:- +full:timer
1 /*-
30 /dts-v1/;
34 compatible = "compulab,trimslice", "nvidia,tegra20";
35 #address-cells = <1>;
36 #size-cells = <1>;
38 interrupt-parent = <&GIC>;
51 SOC: tegra20@0 {
52 #address-cells = <1>;
53 #size-cells = <1>;
54 compatible = "simple-bus";
56 bus-frequency = <0>;
58 GIC: interrupt-controller@50041000 {
60 interrupt-controller;
61 #address-cells = <0>;
62 #interrupt-cells = <1>;
67 compatible = "arm,mpcore-timers";
68 clock-frequency = < 50040200 >;
69 #address-cells = <1>;
70 #size-cells = <0>;
71 reg = < 0x50040200 0x100 >, /* Global Timer Registers */
72 < 0x50040600 0x100 >; /* Private Timer Registers */
74 interrupt-parent = < &GIC >;
78 compatible = "nvidia,tegra2-timer";
81 interrupt-parent = <&GIC>;
85 compatible = "nvidia,tegra2-timer";
88 interrupt-parent = <&GIC>;
92 compatible = "nvidia,tegra2-timestamp";
97 compatible = "nvidia,tegra2-timer";
100 interrupt-parent = <&GIC>;
104 compatible = "nvidia,tegra2-timer";
107 interrupt-parent = <&GIC>;
113 reg-shift = <2>;
115 interrupt-parent = <&GIC>;
116 clock-frequency = < 215654400 >;
122 reg-shift = <2>;
124 interrupt-parent = <&GIC>;
125 clock-frequency = < 215654400 >;
131 reg-shift = <2>;
133 interrupt-parent = <&GIC>;
134 clock-frequency = < 215654400 >;